# LTC3637: Capacitor in parallel with Feedback Resistor to Reduce Ripple?

dulcevida has been answering my questions regarding my LT8362 SEPIC power supply design, and he suggested I ask this related question in a new post since it deals with the LTC3637.  But please note I will talk about both part numbers in this post, so please do not confuse the part numbers.

When reviewing the LT8362 datasheet's "Typical Application" circuits, I see that all of them have a capacitor labeled C6 or C7 valued at 4.7pF in parallel with Feedback (FBX) resistor R1:

http://www.analog.com/media/en/technical-documentation/data-sheets/8362fa.pdf

The purpose of that 4.7pF capacitor is not clearly explained in the LT8362 datasheet.

I have another design (24V input, 12V output, 1A) based on the LTC3637 that has a single 12V/1A output. My design is quite similar to the Typical Application circuit shown at the bottom left of the first page in the LTC3637 datasheet:

The simulated output voltage of my LTC3637 circuit is as follows:

OUTPUT Voltage & Current (LTspice):

I have been pondering output ripple and how to reduce it.  I use a Ferrite Bead to eliminate the HF spikes, and the resulting ripple, depending on load, is about 81mVp-p.  Since a 4.7pF capacitor is used in all the example LT8362 example circuits, I wanted to see how output ripple would be affected in my LTC3637 circuit if I added that 4.7pF capacitor across the feedback resistor R1 (200k-ohm).  I've not yet built the circuit.  I am simply running LTspice simulations at this stage.  The simulation result was that output voltage was slightly reduced but ripple was also significantly reduced:

OUTPUT Voltage & Current (LTspice):

I then increased that capacitance value ten-fold to 47pF. The simulated output voltage drops further to +11.26V, but the ripple is only 1/5th of what it is without the capacitance.  In other words, there is more ripple when I do not use the capacitance across R1.  To prevent the output voltage drop, I increased R1 from 200k to 220k and kept the 47pF in parallel with it, which resulted in a simulated output voltage of 12.1V and roughly the same ripple reduction, as you can see here:

CIRCUIT (LTspice):

OUTPUT Voltage & Current (LTspice):

My question is this. I would like to know why the 4.7pF capacitance is used across FBX resistor R1 in all the LT8362 example application circuits when it is not used at all in the LTC3637 examples.  Can I safely use such a 47pF capacitance across R1 in my LTC3637 BUCK regulator circuit, or would it cause instability?  I am not seeing any obvious caveats in my LTspice simulation of the LTC3637 circuit while using a 47pF capacitance across R1.  Once again, output ripple is reduced significantly (in LTspice simulations) when using 47pF in parallel with R1.  Could you tell me what the caveats, if any, there are to adding 47pF of capacitance across R1?

Thank you.

Parents
• It's not necessary to add the 47pF for the LTC3637. If the converter is built correctly, this cap does little to the output ripple. If you add the cap, normally the loop should not become unstable. Just carefully evaluate the prototype board. (You may have an optional position for your board for this if you want.)

For the LTC3637, 4-layer board is not absolutely necessary.

Please follow the data sheet instructions, and the board should work ok. (There are many layout considerations, tricks, etc. Those may be too many/too longer and not suitable to discuss here). Ask for a local ADI FAE's help if there is a layout problem. Thanks.

Reply
• It's not necessary to add the 47pF for the LTC3637. If the converter is built correctly, this cap does little to the output ripple. If you add the cap, normally the loop should not become unstable. Just carefully evaluate the prototype board. (You may have an optional position for your board for this if you want.)

For the LTC3637, 4-layer board is not absolutely necessary.

Please follow the data sheet instructions, and the board should work ok. (There are many layout considerations, tricks, etc. Those may be too many/too longer and not suitable to discuss here). Ask for a local ADI FAE's help if there is a layout problem. Thanks.

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