LTC3637: Capacitor in parallel with Feedback Resistor to Reduce Ripple?

dulcevida has been answering my questions regarding my LT8362 SEPIC power supply design, and he suggested I ask this related question in a new post since it deals with the LTC3637.  But please note I will talk about both part numbers in this post, so please do not confuse the part numbers.

When reviewing the LT8362 datasheet's "Typical Application" circuits, I see that all of them have a capacitor labeled C6 or C7 valued at 4.7pF in parallel with Feedback (FBX) resistor R1:

http://www.analog.com/media/en/technical-documentation/data-sheets/8362fa.pdf 

The purpose of that 4.7pF capacitor is not clearly explained in the LT8362 datasheet.

I have another design (24V input, 12V output, 1A) based on the LTC3637 that has a single 12V/1A output. My design is quite similar to the Typical Application circuit shown at the bottom left of the first page in the LTC3637 datasheet:

http://www.analog.com/media/en/technical-documentation/data-sheets/3637fa.pdf 

The simulated output voltage of my LTC3637 circuit is as follows:

OUTPUT Voltage & Current (LTspice):

https://cl.ly/qwOF/Image%202018-04-17%20at%205.48.39%20PM.png 

I have been pondering output ripple and how to reduce it.  I use a Ferrite Bead to eliminate the HF spikes, and the resulting ripple, depending on load, is about 81mVp-p.  Since a 4.7pF capacitor is used in all the example LT8362 example circuits, I wanted to see how output ripple would be affected in my LTC3637 circuit if I added that 4.7pF capacitor across the feedback resistor R1 (200k-ohm).  I've not yet built the circuit.  I am simply running LTspice simulations at this stage.  The simulation result was that output voltage was slightly reduced but ripple was also significantly reduced:

OUTPUT Voltage & Current (LTspice):

https://cl.ly/qvPM/Image%202018-04-17%20at%205.54.29%20PM.png 

I then increased that capacitance value ten-fold to 47pF. The simulated output voltage drops further to +11.26V, but the ripple is only 1/5th of what it is without the capacitance.  In other words, there is more ripple when I do not use the capacitance across R1.  To prevent the output voltage drop, I increased R1 from 200k to 220k and kept the 47pF in parallel with it, which resulted in a simulated output voltage of 12.1V and roughly the same ripple reduction, as you can see here:

CIRCUIT (LTspice):

https://cl.ly/qwKg/Image%202018-04-17%20at%205.46.47%20PM.png 

OUTPUT Voltage & Current (LTspice):

https://cl.ly/qw2S/Image%202018-04-17%20at%205.52.17%20PM.png 

My question is this. I would like to know why the 4.7pF capacitance is used across FBX resistor R1 in all the LT8362 example application circuits when it is not used at all in the LTC3637 examples.  Can I safely use such a 47pF capacitance across R1 in my LTC3637 BUCK regulator circuit, or would it cause instability?  I am not seeing any obvious caveats in my LTspice simulation of the LTC3637 circuit while using a 47pF capacitance across R1.  Once again, output ripple is reduced significantly (in LTspice simulations) when using 47pF in parallel with R1.  Could you tell me what the caveats, if any, there are to adding 47pF of capacitance across R1?

Thank you.

  • It's been 24 hours and no replies, so perhaps my opening question is too difficult?  Well, while you are pondering that question, I have another 2 questions might be easier for you.  

    QUESTION#1

    The DC2056A is the LTC3637 Evaluation Kit.  The Design Files are downloadable here:

    DC2056A - Design Files

    Not having designed a switch-mode power supply before, and not being a PCB designer, I had my PCB guy in Taiwan take my design schematic and review those DC2056A design files.  We now have a PCB layout completed, but it's 2-layer, not the 4-layer board used in the Evaluation Kit.  Is 4-layers absolutely necessary?  

    My PCB design is a revision of an earlier design which used a linear power supply, which also was 2-layer.  Four-layer boards are more expensive, so if they are not absolutely needed for switch-mode power supply designs, I'd prefer to stick with 2-layer.  I would therefore appreciate hearing your thoughts on my use of a 2-layer PCB with my LTC3637 design.  I am happy to show you the PCB layout if you like, although I would prefer to password protect the ZIP archive of my design files if I post them here, sending the password to you by email or another means, if possible.

    QUESTION#2

    I would also like to know why the LTC3637 Evaluation Kit PCB layout uses a square cut-out on all layers beneath its L1 10uH coil, whereas some of your other switcher controllers like the LT8362 have evaluation kits that don't have the cut-out at all and just put ground planes beneath the coil.  The evaluation kit follows the PC Board Checklist, Point-4, given on page 19 of the LTC3637 datasheet which says, "Flood all unused area on all layers with copper except for the area under the inductor."  I would think that if the cut-out is necessary for the main coil in LTC3637 designs, the same thinking should hold true for the primary coil when using other controllers too, like the LT8362. Could you please shed some light on the seemingly inconsistent PCB layouts?  Should I keep the area cleared under my coupled-inductor SEPIC LT8362 design too?

    I look forward to your reply regarding my opening post question and the 2 questions in this post.

    Thank you.

  • Chaz,

    Thank you for your helpful reply.  

    Basically you are saying that LTspice is giving me incorrect information in terms of output ripple.  "Garbage in, garbage out" holds true and sims aren't perfect, but what you said does have me curious.  You see, when I add a 47pF cap across R1 in LTspice, ripple is noticeably reduced, even if I use a small value like 4.7pF.  Using 47pF (ten times larger) reduces ripple to only 25% of what it is without the capacitor, in LTspice.  

    I am putting the finishing touches on our PCB layout now (we've not built any PCB yet), and I am pondering the addition of 2 pads for a 47pF cap in parallel with R1.  But if you are strongly saying that the LTspice output is in error with regard to ripple reduction due to a cap across R1, then I will leave out the 47pF cap.  I mainly wrote my opening post to see if adding a 47pF cap across R1 would cause instability, but you replied that it would not.  Even so, to ensure you see exactly what I am seeing in LTspice and can therefore comment more specifically on that output ripple, here is a ZIP archive containing my LTspice design and all required files.  (Please rename your "ISO16750-2.lib" so you don't replace yours with mine, seeing I edited mine to make it simulate faster.)

    I look forward to your reply.

  • 0
    •  Analog Employees 
    on Apr 20, 2018 1:25 AM

    It's not necessary to add the 47pF for the LTC3637. If the converter is built correctly, this cap does little to the output ripple. If you add the cap, normally the loop should not become unstable. Just carefully evaluate the prototype board. (You may have an optional position for your board for this if you want.)

    For the LTC3637, 4-layer board is not absolutely necessary.

    Please follow the data sheet instructions, and the board should work ok. (There are many layout considerations, tricks, etc. Those may be too many/too longer and not suitable to discuss here). Ask for a local ADI FAE's help if there is a layout problem. Thanks.

  • Chaz,

    I wanted to follow-up to confirm if you have taken a few moments to download my ZIP archive and reproduce my findings (regarding ripple reduction) in your own copy of LTspice?  dulcevida very kindly did that with a separate (unrelated) problem I reported to him about the LT8362.  His making time to do that was very helpful and greatly appreciated.  And since this is a public forum, the information will no doubt help others who come across it as well.

    Please know I understand how busy you must be, and I am aware you would prefer me to speak to a local ADI FAE.  Even so, we contract with a factory in Taiwan to manufacture our products and we rely on them to source parts for the schematics we design, and hence our "local ADI FAE" is in Taiwan; and since I do not speak Chinese, I would prefer to speak to you here in English, at least on this technical matter where you would surely know more than they would.

    To reiterate, I am simply curious about reducing output Ripple by adding a 47pF cap across R1, and if you would please download and simulate my files in LTspice, you will see precisely what I see.  I apologize if you feel I am pressuring you, but I only seek a little feedback from you on that one matter, seeing you are the applications engineer for the LTC3637.  Reducing output ripple using that 47pF capacitor across R1 is the only question I intend to put forth to you, and I won't continue to ask an endless string of questions thereafter.  I simply want to hear your professional and experienced opinion on the capacitor across R1, based on what you see in LTspice and based on your extensive knowledge of the LTC3637, which surely matches or transcends what is written in the LTC3637 datasheet.  It would probably take 15 to 30 minutes of your time simulate and compose your thoughts; and if your posts here will help anyone else who finds this thread and has similar questions about the LTC3637, ensuring your time is not wasted.

    Many thanks for your time and kind consideration.   I look forward to your reply.

  • Chaz,

    Thank you for sharing your thoughts.

    I have simulated a light load condition of only 1mA, going as low as 500uA.  The ripple on the +12V output, as measured after my Ferrite Bead, was only 22mVp-p when using the 47pF cap across R1=220k and a 1mA load.  I then ran another simulation using varying loads of 3mA to 750mA (the same loads setup in my ZIP archive), and the resulting ripple (after the BEAD) was no more than 18mVp-p.  Without the 47pF cap and using R1=200k, the output ripple (after the BEAD) measures about 81Vp-p in LTspice using the same varying loads, and about 88mVp-p with a 1mA light load.  By the way, I am using a ferrite BEAD because in the LTspice simulations because the amplitude of the HF spikes are quite high (400mVp-p for light loads of 1mA or 500uA, with or without that 47pF cap) and the BEAD does a good job (at least, in simulation) of pretty much eliminating those spikes, allowing my eyes to actually see the ripple.

    Another interesting thing to note is that if the 47pF capacitor is edited in LTspice so that its "Parallel Resistance" is set to be 50mega or larger, then R1 can be left at 200k because there is then no drop in output voltage.

    Also of note, the larger the capacitance across R1, the lower the output ripple becomes.  That capacitance across R1 works so laughably well in LTspice that it makes me wonder if the output isn't just a misleading quirk of LTspice.   

    Honestly, if ripple wasn't 81mVp-p on the 12V output without the cap across R1 (as per LTspice), I wouldn't even waste my time thinking about this; but if there's an opportunity to reduce that ripple significantly without causing instability, I wish to investigate it.  As such, I would once again like to encourage you to download my ZIP archive and run that in your own copy of LTspice.  Perhaps you then might have more specific thoughts to share.

    I look forward to your reply.