I'm looking at the ADM1272 and a single PSMN4R8-100BSE (as used in the ADM1272 EVAL board) for a couple of +48V based projects, and I have a couple of questions. The first project is a cellular modem which for reception reasons needs to be movable while being powered by the conditioned +48V source from the "base" system, so I've got up to ~300 feet max (in theory, likely to be significantly less, along the lines of 6 feet) of AWG 18 wire feeding power. I want to use the ADM1272 to handle inrush current when the modem is inevitably plugged and un-plugged while the system is active, and it's not a bad idea to have a circuit breaker feature as well. Maximum estimated power draw of the modem is ~16W. I'm shooting for a very mild 500mA startup current limit, and an arbitrarily over-sized 1A run current limit, both of which fall within the DC SOA at 50V.
1) GND, AGND, AGND1 - On the eval schematic, Vin, Vout and the protection diodes are referenced to GND, a majority of the components related to the ADM1272 are referenced to AGND, and some are referenced to AGND1. AGND and AGND1 are connected to GND through jumpers LK1 and LK2 and AGND1 seems to be more discrete traces than an actual plane. What exactly is the theory or guidelines used to determine which semi-isolated ground plane AGND or AGND1 should be used for which components? Is it sufficient for me to design a single semi-isolated ground plane for the ADM1272 and components and tie that to the main board ground at a single point or is it necessary to isolate for example the VCP pin's R+C components and the Vcc bypass cap? A couple of paragraphs and a diagram or two on board layout would be a nice addition to the datasheet.
2) MCB Pin - I don't want to mask the severe OC shutdown. The datasheet says there's an internal 1MOhm pull-down on the pin, is that sufficient to where I may leave the pin unconnected or would you recommend a 10k or 20k external pull-down to ground? On a side note, I plan on using dv/dt startup for the 500mA current limit but if I had chosen to use the ISTART limit instead (which I assume would not fault as long as the ESTART SOA RC timer was adequate) there is no mention of what would need to be done with the unused DVDT pin (unconnected? Pulled up or down?).
3) ESTART & EFAULT pins - The datasheet states "Through analysis and manipulations of the SOA curves, for a given fixed current, an RC configuration from EFAULT/ESTART to GND can provide a solution to ensure the voltage on the pin reaches 1 V before the SOA is exceeded." I believe it. However, I am in need of a more detailed design procedure as it's new to me. For this my first design given the eval startup current limit of 4A and my limit of 500mA and the fact that I'm using the same MOSFET, I assume I'd be safe with the values shown for the ESTART pin, and even with a single MOSFET my 1A current limit as opposed to 30A (15A per-MOSFET) I could probably get by with the values shown for EFAULT. In fact since I'm well within the DC SOA in both cases I assume I don't really need either the ESTART or EFAULT values to be dialed in, but what exactly should I do with them? Plus I'd like to know how to go about calculating the required values for my next designs...
4) UVL, UVH and OV - Minor question really which shows my lack of hands-on experience here, how important is the 100nF cap filter across the bottom resistor of the divider? Given a 48V nominal target voltage (and I2R losses of about 4.2V @ 330 feet of cable so ~43V worst case) and a UVH target of 40V am I likely to see enough noise on the cable to raise havoc with the UV/OV dividers? The "next" designs will be multiple FPGA cards in a 48V backplane, is that environment more or less susceptible to noise causing problems? I'm not against a few extra caps for a more robust design, but if in practice they've proven to be only rarely useful in extreme cases then I may rather minimize the real estate involved. I'll guess the answer is "it depends", I'm hoping maybe for some advice based on previous experience of DC-DC switchers polluting an otherwise nice, quiet backplane power rail...
I think that's it for now at least. Any advice is appreciated.
I would like to know the procedure to set the EFAULT & ESTART RC networks based on SOA of different MOSFETs