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ADP5080 I2C Timing


My customer is considering using ADP 5080 and received a question.

REG 2 is used for VDDIO and another DCDC regulator is used for I2C pull-up.
When the EN pin was set to H, the power supply sequence did not start and was not output.

# 1   I referred to "If VDDIO is supplied by VREG2, SCL must be high impedance until VREG2 rises above the POR

        threshold." described in the data sheet.

        How can I make SCL high impedance?

        Should I pull up SCL to H?

#2    Is there a sequence diagram showing the timing of VDDIO and I2C startup?

Best Regards,


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