ADP5080 I2C Timing


My customer is considering using ADP 5080 and received a question.

REG 2 is used for VDDIO and another DCDC regulator is used for I2C pull-up.
When the EN pin was set to H, the power supply sequence did not start and was not output.

# 1   I referred to "If VDDIO is supplied by VREG2, SCL must be high impedance until VREG2 rises above the POR

        threshold." described in the data sheet.

        How can I make SCL high impedance?

        Should I pull up SCL to H?

#2    Is there a sequence diagram showing the timing of VDDIO and I2C startup?

Best Regards,


  • 0
    •  Analog Employees 
    on May 4, 2018 7:03 PM over 2 years ago

    Hi Yuya,

    For # 1 item,  if you have connected VREG2 to VDDIO , please must connect to VDDIO to the input of pull up of SCL/SDA. and then you don't need to take care of this sequence, since the pull up voltage will be high impedance.

    The important thing is that no input supply for VDDIO before POR event when you connect VREG2 to VDDIO.


    For #2 item, we don't disclose the internal power up sequence for VDDIO.

    Please contact local ADI FAE directly, if you have more questions. 



  • Hi, takahiko

    Thank you for your answer.

    I understood that it is important not to be applied to VDDIO before POR event.
    Also, I understand that VDDIO's internal power-on sequence is not disclosed.