We put two LTM4623 in parallel and are getting a persistent ~30kHz ripple of ~25mV out. Any ideas why? We set to 3.9V and use external sync at 2MHz. We feel we followed the data sheet design & layout instructions quite closely. We're gonna try piling on Cin & Cout. Is it worth trying other things we see on the 2171A Demo Bd: 2.2uF on IntVcc; a RC LPF from Vin to SVin; & a cap parallel to the Feedback resistor? Thanks!
I didn’t see any issue in the layout images you provided. I checked your application out on the bench and using 2 demo boards paralleled and set up with your component configuration I was able to reproduce the low frequency output oscillation you saw.
Internally the LTM4623 uses a monolithic constant on-time valley current mode regulator, the clock turns on the top fet with programmed on-time then bottom fet turns on until valley current trips the current comparator turning off the bottom fet and re-starting the cycle. Switching jitter (in this case frequency jitter) can be induced on these types of parts by adding noise when the valley current is about to trip the current comparator. Jitter shows up on the output as a lower frequency ‘oscillation’. The switch edges rise and fall pretty quickly so there is high dV/dt noise at these edges. In your application with the duty cycle is ~33% and in a clocking configuration where the two phases are phase shifted by 180 deg a switch edges of the one phase fall in the vicinity of the rising switch edge (ie where current comparator is to trip) the other phase leading to the jitter / output ‘oscillation’.
Generally the jitter can be improved by increasing the gain margin (ie increasing attenuation of high frequency noise in the loop for example with an added cap from COMP pin to GND) or by speeding up the loop enough so it can help respond to the noise disturbance (ie increasing feed-forward capacitance between Vout and FB pins). Otherwise it would be recommended to try to keep the other phase’s switch edges from the vicinity of the rising edge of this rising switch edge. In your case it would be recommended to feed the external clock signal to both modules’ CLKIN pins so their switching is aligned with no phase shift in order to prevent switch edge noise showing up at the worst time.
FYI attached is some bench data to compare output ripple with 0 deg phase shift vs. 180 deg phase shift, showing the improvement when the external clock is provided directly to both phases. I hope this may be an acceptable solution for you.
While putting two LTM4623 in parallel, what if I connect the CLKOUT of first to CLKIN of the next but do not connect any external CLK to CLKIN of first LTM4623?
Would I still be able to achieve parallel load sharing? And LTM4623 in LTPowerCad is not listed as a Polyphase device, so how do I simulate parallel behavior of LTM4623?
it is Ok if you do not to connect any external clk to the pin CLKIN of the first LTM4623 as shown in Figure. 2 of the datasheet
You can use LTspice XVII for your simulation