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LTM4608A External FSW Synchronization CLK Characteristics

Hello ADI Community,

I have another question regarding the LTM4608A component.

When the CLKIN pin of the LTM4608A is being utilized for external switching frequency synchronization, what are the required characteristics of the external clock signal? For example, what is the desired logic level, Vinh & Vinl thresholds, duty cycle, timing constraints, etc.? 

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  • We use a 0V - 2V clock. Your clock can differ, as long as it meets the following constraints:

    Vin_high threshold:  1.2V

    Vin_low threshold:  0.3V

    Minimum ON-time:  100ns

    Minimum OFF-time:  0ns (There is no minimum OFF-time constraint.)

    Frequency Range:  0.75 - 2.25 MHz

    Vabs_max:  Vin

    Vabs_min:  -0.3V

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  • We use a 0V - 2V clock. Your clock can differ, as long as it meets the following constraints:

    Vin_high threshold:  1.2V

    Vin_low threshold:  0.3V

    Minimum ON-time:  100ns

    Minimum OFF-time:  0ns (There is no minimum OFF-time constraint.)

    Frequency Range:  0.75 - 2.25 MHz

    Vabs_max:  Vin

    Vabs_min:  -0.3V

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