I am using LTC4367 as inrush current limiter for my applicationwith IN of 36V. I am using a single power MOSFET as indicated in the attached LTSpice schematic to limit the inrush current into 4 HV electrolytic capacitors each of 560uF. There is no load connected at the output as the next converter stage is undervoltage protected with UV= 88% of VDC.In order to limit the current to around 1.2A, I am using a 65nF capacitor at the gate shown. However, I cannot assure if the power MOSFET used (IPB048N15N5_L1) will still work in SOA because as shown in the waveform attached, both Id and Vds of the power MOSFET are ramping with time, thus I am not sure which time period at which voltage/current I should consider to check the SOA of the power MOSFET. The issue is that the using of Cgate of 65nF does limit the inrush current, however it prolongs the linear region operation of the power MOSFET.Any comment please?ThanksP.S: The LTSpice schematic can be sent for testing.
One of checking the SOA would be to take highest Vds (36V), inrush current (0.8A as per waveforms) and time it took to charge the caps (~100ms as per waveforms) and check the SOA curve if this FET can…
Hello experts, Can anyone help me in this question please?Fil ezadmin
One of checking the SOA would be to take highest Vds (36V), inrush current (0.8A as per waveforms) and time it took to charge the caps (~100ms as per waveforms) and check the SOA curve if this FET can handle this stress. As per SOA curve of IPB048N15N5, it should be fine but SOA curves are usually taken by placing MOSFET on a cold plate. Make sure to add a lot of Cu on your board which then connects to the exposed pad of the FET.
Thanks for your help. Yes, the MOSFET is exposed well down to the bottom layer with thermal very close thermal vias.