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Reg : LTC2924 - 200us delay - Simulation - Query

We plan to use LTC2924 in our design, In the blog it is suggested as 200us can be achieved by using 1nF capacitor.

https://www.analog.com/en/technical-articles/flexible-power-supply-sequencing-monitoring.html

But in my simulation, its taking around ~470us. How I can reduce this value to  <= 200us. I need each power rail need to release within 200us delay.

The simulation file attached for your end verification.

Measured using 1nF capacitor : 4885.Power_sequencer_2ICs_200us delay (1).asc

 i hope, In the simulation tool will  not take parasitics for analysis. Since 100nF capacitor value, i am getting 20ms delay exactly. (Refer the second image)
Measurement using 100nF capacitor : 

Please provide your comments

  • Hi Selvakumar,

    The timer is running for 200usec only as programmed by the cap on the TIMER pin. After every 200us, OUTx pin starts to pull up with 10uA. The additional time that you noticed is the time it takes for MOSFET to enhance. See the following waveforms. Notice that as soon as TIMER expires, Vgs starts to pull up. But it does take some finite time to enhance the MOSFET which is showing up as added delay.