Hi ,
I have a ADM1272 Eva Board. It is not clearly information related Estart and Efault pins. The subject has been opened before. But nothing has been explained. Which formulas are applied here? Thanks for your help.
Hi ,
I have a ADM1272 Eva Board. It is not clearly information related Estart and Efault pins. The subject has been opened before. But nothing has been explained. Which formulas are applied here? Thanks for your help.
Hi Yusuf,
The easiest way to think about the EFAULT and ESTART pins of the ADM1272 is as translating FET stress into voltage, which is then used to determine when to shut down. These pins output a current that approximates the FET stress (proportional to Vds while the current is limited by the clamp). If you build an equivalent electrical model of your FET (A Cauer model) then the pin voltage will hit 1V as the FET junction temperature reaches its limit. Usually it is sufficient to simplify this equivalent circuit to one capacitor and two resistors, and look at the FET SOA diagram to determine the sizes of these components. Consider the following circuit.
Supplied by a fixed current (a constant Vds across the FET) you can imagine three possibilities:
1) ESTART current gradually charges up the capacitor to 1V and the ADM1272 turns off. This is similar to a "normal" timer function in a hotswap. Calculate the value of C that produces this time out for a given FET SOA stress level (Vds and I), assuming R2 is infinite and R1 is 0.
2) I(R1) is large enough to immediately reach 1V regardless of voltage across the capacitor. This is the case for large FET Vds, and represents high stress situations. Calculate the value of R1 to reach much or all of the 1V threshold without charging the capacitor. This sets an upper limit on allowable FET Vds. Usually you won't use a resistor that large, but something smaller that requires some voltage across both R1 and C to time out.
3) For lower stress situations (10ms and 100ms lines on the SOA plot) you can slow-down the ESTART and EFAULT response by adding R2. This draws away some of the current charging the cap, and makes it take longer to reach 1V. You are setting the R2*C time constant to add delay. Be careful, though, because at some low value of ESTART current the pin voltage will not be able to rise to 1V at all, and the timer will never elapse.
Reasonable values for each component lie in these ranges:
0 < R1 < 50k (default to 10k if unsure)
100k < R2 < infinity (default to inf. if unsure)
4.7nF < C < 100nF (default to 22nF if unsure)
The same type of circuit can be used for both ESTART and EFAULT. You can set one to work with the ISTART limit and one to work with the ISET limit. As you can see, this is an art form, rather than a set of closed-form equations. Each FET SOA diagram, coupled with the operating conditions of your system, will dictate your EFAULT and ESTART circuit. I recommend using a SPICE simulator to visualize the delays for various values of EFAULT/ESTART pin current and cross-reference that to SOA diagram stress levels.
Thanks!
Nathan
Hi Yusuf,
The easiest way to think about the EFAULT and ESTART pins of the ADM1272 is as translating FET stress into voltage, which is then used to determine when to shut down. These pins output a current that approximates the FET stress (proportional to Vds while the current is limited by the clamp). If you build an equivalent electrical model of your FET (A Cauer model) then the pin voltage will hit 1V as the FET junction temperature reaches its limit. Usually it is sufficient to simplify this equivalent circuit to one capacitor and two resistors, and look at the FET SOA diagram to determine the sizes of these components. Consider the following circuit.
Supplied by a fixed current (a constant Vds across the FET) you can imagine three possibilities:
1) ESTART current gradually charges up the capacitor to 1V and the ADM1272 turns off. This is similar to a "normal" timer function in a hotswap. Calculate the value of C that produces this time out for a given FET SOA stress level (Vds and I), assuming R2 is infinite and R1 is 0.
2) I(R1) is large enough to immediately reach 1V regardless of voltage across the capacitor. This is the case for large FET Vds, and represents high stress situations. Calculate the value of R1 to reach much or all of the 1V threshold without charging the capacitor. This sets an upper limit on allowable FET Vds. Usually you won't use a resistor that large, but something smaller that requires some voltage across both R1 and C to time out.
3) For lower stress situations (10ms and 100ms lines on the SOA plot) you can slow-down the ESTART and EFAULT response by adding R2. This draws away some of the current charging the cap, and makes it take longer to reach 1V. You are setting the R2*C time constant to add delay. Be careful, though, because at some low value of ESTART current the pin voltage will not be able to rise to 1V at all, and the timer will never elapse.
Reasonable values for each component lie in these ranges:
0 < R1 < 50k (default to 10k if unsure)
100k < R2 < infinity (default to inf. if unsure)
4.7nF < C < 100nF (default to 22nF if unsure)
The same type of circuit can be used for both ESTART and EFAULT. You can set one to work with the ISTART limit and one to work with the ISET limit. As you can see, this is an art form, rather than a set of closed-form equations. Each FET SOA diagram, coupled with the operating conditions of your system, will dictate your EFAULT and ESTART circuit. I recommend using a SPICE simulator to visualize the delays for various values of EFAULT/ESTART pin current and cross-reference that to SOA diagram stress levels.
Thanks!
Nathan