LT8362 suggested boost layout lacks a detail - and is it really a good suggestion?

In the datasheet is this suggested layout for LT8362 as boost converter as shown here:

I have highlighted the SW node in red.

Question: There is no connection between the two red nodes (SW). I assume it is implicit that it is connected on another layer and simply not shown here. This is the reason for all the via's.  The number of via's also implies that this hidden connection is of a comparable width. 

Are these observations and conclusions correct?

I would assume that calling this a "suggested layout" also implies optimal layout in some sense.

But this layout has SW node with via's and a trace passing under the GND planes. This adds capacity to the SW node and the via's perforates the GND plane which deteriorate EMI. This node has up to 2MHz and possibly several 10's of volt.

So, this brings me to my real question: Why is this layout suggested because it breaks the traditional wisdom of keeping the SW node small in area and with low capacity?

Below I have added my take on the layout using the same component footprints:


  1. The sw node is minimal in area.
  2. The sw node has no via's
  3. The likewise critical loop with spiky current through the switch-diode-Cout is still short (unchanged)
  4. The less critical loop through switch-Inductor-Cin is shorter than original. Less critical because the inductor filters the current spikes.
  5. There is a connection (in red) on another layer from Vin to pin 3. This connection is low current and quiet thus no problem to pass like that on another layer.

Any comments to these considerations are welcomed - especially from the one who wrote this part of the datasheet.


  • +1
    •  Analog Employees 
    on Apr 14, 2020 1:47 AM

    Hello Larsen,

    Unfortunately, the person who wrote this part of the datasheet might not be able to respond to this posting. 

    You make a great point with your suggestion, particularly if EMI is a concern. 

    The hot loop, comprised of the switch node, the diode and the output capacitor, is similar on both, and this loop is more critical for EMI.

     I think the suggested layout was suggested to address other important issues, and EMI was not on top of the list. 

    There are two applications in the datasheet that were tested for EMI, and both used your layout approach, so I agree with you 100%.