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LTC3643 bottom switch is broken

Hi There,

I have a question regarding a charge process in LTC3643.

Is there any situation that a bottom switch of LTC3643 is broken during charge process?

It is described in the datasheet that maximum charge current is limited up to 2A, therefor internal MOSFET should be protected in the charge process.

If we use a current limit resistor of 0.01ohm (charge current could be 2A), bottom switch is broken. However we use the current limit resistor of 0.1ohm(charge current could be 0.4A), charge process is completed correctly. Load current of LTC3643 is 100mA for PMIC. Our LTC3643 schematic is as attached.

When we tested boost/buck mode operation in the DC2220A demo board same as our configuration, that is worked correctly.

Input voltage = 5.5V

Vcap = 39.5V

Output volgate = 5.5V

PFI Rising voltage = 5.029V / Falling voltage = 4.571V

Best Regards,

Kumac

Parents
  • Hello, I am not aware of any reason why the bottom SW might break during charge unless the top FBCAP resistor is open or the bottom FBCAP resistor is shorted. I did not see anything obvious with the schematic.

    Regards, Marty

  • Hi Marty,

    Thank you for your reply.

    I understand the schematic looks good and there is no reason without FBCAP resistor failure.

    Is there possibility that the bottom SW is failed caused by following reason?

    (1) Inductor saturation occurred.

    (2) Input power current or transient spec is not enough. (+5P5V_VIN in the schematic is supplied from DC-DC converter such as +5.5V/2.5A. I use TI's TPS54240 that is non-synchronous and running at 478kHz. I know it can not be supported by ADI. I will try to use ADI's LT8609A evaluation board instead of TPS54240 for input power supply.)

    Best Regards,

    Kumac

  • Hi Kumac, The inductor shown on the schematic has a soft saturation curve and still has plenty of inductance over 3A.

    If the input supply droops below the input UVLO or even below the operating range because of a large current transient will not cause the bottom FET to fail. These are typically test that are done prior to release of the part. 

    Thanks,

    Marty

  • Hi Marty,

    Thank you for your answer.

    I understand, the bottom SW will not be failed easily because LTC3643 have protection circuit such as over current or heat protection.

    When I cut off the power in our board I got a unexpected high voltage on +5P5V_OUT as attached. +5P5V_IN is turned off at -1ms and voltage is decreased until trigger point. After this phenomenon occurred, the bottom SW was failed and I checked a resistance following pins.

    Between SW pin and GND is 0ohm.

    Between INDIS pin and VIN pin is 0ohm.

    According to work correctly in the evaluation board, our PCB layout may have any problem. Is there any case that PCB layout cause above phenomenon?

    Best Regards,

    Kumac

  • Hi, I have an additional information regarding our PCB layout. Our PCB have 6 layers and LTC3643 is placed on bottom side. I found a pulse noise that have about 3V peak on HVBC_ILIM pin. It could be caused by our PCB layout. HVBC_ILIM signal is passed through under the Inductor(L2). There is no GND plane under the inductor on layer 5. I put our PCB layout as PDF file. I will update waveform of the pulse noise tomorrow.

    Thank you,

    Kumac

    PDF

    PDF

    PDF

  • Hi Kumac, This is interesting. I agree that the layout with the inductor over these traces are not ideal, but I am not convinced this is the problem. Is it possible to obtain a scope shot of VIN, the SW node and if you can get a pull up on PFO that also?

    Thanks, Marty

Reply
  • Hi Kumac, This is interesting. I agree that the layout with the inductor over these traces are not ideal, but I am not convinced this is the problem. Is it possible to obtain a scope shot of VIN, the SW node and if you can get a pull up on PFO that also?

    Thanks, Marty

Children
  • Hi Marty,

    I probed ILIM, SW node, VIN and PFO during burst mode operation in our board. I found a pulse noise on ILIM same as SW node pulse. I tried to connect ILIM to GND then I can not see any noise on ILIM. I will check whether our issue is resolved by this solution or not. In addition, I found the pulse noise same as our board in the evaluation board that is probed at JP2.

    Best Regards,

    Kumac

    (1) ILIM waveform

    (2) SW node waveform

    (3) ILIM waveform in the evaluation board (JP2)

    (4) PFO(ch2) and VIN(ch3) at power lost

    (5) PFO and VIN at power return

  • Hi Kumac, Thank you for the scope shots. How short was the GND for the scope probe for these shots? Even a couple centimeter GND probe can pick up some noise. Regardless of the extra noise pickup the ILIM wave form is very large. I am curious to learn if GNDing the pin helps. 

    Thanks, Marty

  • Hi Marty,

    I probed ILIM again using short GND less 15mm. In addition, I cut the ILIM trace near the pin as attached layout. ILIM pin is just floating but the pulse noise still exist. It looks ILIM pin leak the pulse noise. ILIM pin in the evaluation board is floating too, but pulse level is lower than our board. I suppose, this difference is caused by weak GND in our PCB.

    Thank you,

    Kumac

    (1) ILIM in our board

    (2) ILIM in the evaluation board

    (3) PCB layout (L6)

    PDF

  • Hi,

    I modified our PCB layout. I moved LTC3643 from bottom to top on the PCB. Our PCB have the following layer stack. As a result LTC3643 is worked correctly. Our problem have been resolved. Thank you for your support.

    L1 Signal

    L2 GND plane

    L3 Signal

    L4 Signal

    L5 VCC plane

    L6 Sgnail

    Best Regards,

    kumac