Hi ADI member,
About LTC3880, we had some questions need your support.
1) See block diagram, 16-BIT ADC with 8:1 MUX in Figure 1, how is there sampling rate for each pipe e.g VSENSE0– and VSENSE0+?
2) Is there any sampling window or sample counts (fixed or programmable) for UVP/OVP? Or just only single count (1T or else) ?
3) Any post-process after ADC sampled within the sampling window or collection of specific sample counts, such as peak-hold for OVP, bottom-hold for UVP, moving average.
4) btw, there is divider resistance circuit 9R: 2R in output of differential amp. (Figure 1), would it be using for hysteresis?
Hi, The ADC update rate is around 90ms through 12 conversions. OV/UV are based on this update rate where Vsense is monitored during its 7.5ms conversion. Each ADC sample is processed through a SINC3 and then sampled with the inverse polarity and subtracted to remove the offset. It is then converted to Linear 16 in the PMBus protocol. The resistance divider sets the gain between Vref and Vout.
Thanks for your reply.
Could you kindly let us know how is the ADC sampling rate, and min. sampling window?
Hi, The ADC updates in a round robin approximately every 90ms. The conversion of 1 of the MUX inputs takes approximately 7.5ms. Thanks, Marvin