LTC3880 sample rate of Vsense

Hi ADI member,

About LTC3880, we had some questions need your support.


1) See block diagram, 16-BIT ADC with 8:1 MUX in Figure 1, how is there sampling rate for each pipe e.g VSENSE0– and VSENSE0+?

2) Is there any sampling window or sample counts (fixed or programmable) for UVP/OVP? Or just only single count (1T or else) ?

3) Any post-process after ADC sampled within the sampling window or collection of specific sample counts, such as peak-hold for OVP, bottom-hold for UVP, moving average.

4) btw, there is divider resistance circuit 9R: 2R in output of differential amp. (Figure 1), would it be using for hysteresis?