Investigating this part in an application as a replacement for TI's LM76202-Q1, due to desire for higher Vin(max) (80V vs 60V).
From the LTC4364 datasheet:
"In all applications the output must be bypassed with at least 22μF low ESR electrolytic (COUT in Figure 1) to stabilize the voltage and current limiting loops, and to minimize capacitive feedthrough of input transients. Total ceramic bypassing of up to one-tenth the total electrolytic capacitance is permissible without compromising performance."
In this application, all ceramic capacitors are highly preferred. With the understanding that this part has not been qualified with all ceramic capacitors and that we will have to perform our own qualification, can you speak to what the concerns are that limit the use of ceramic to 10% of total capacitance? Is the concern overly-low ESR (which can potentially be addressed by adding series resistance to the capacitance), is the concern insufficient total capacitance due to DC biasing (which can potentially be addressed with sufficient capacitance at the Vout(max) design point), or something else?
You can add series resistance to the ceramic capacitance. Please see the DC2027A-A/-B (LTC4364-1/-2 demo board) schematic: https://www.analog.com/media/en/technical-documentation/eval-board-schematic/2027asch…
You can add series resistance to the ceramic capacitance. Please see the DC2027A-A/-B (LTC4364-1/-2 demo board) schematic: https://www.analog.com/media/en/technical-documentation/eval-board-schematic/2027asch.pdf
It looks like that board is only populating 10 uF (minus a bit for DC bias), considerably less than the 22 uF spec'd in datasheet -- can you speak to whether that's acceptable / successful?
It works for the demo board but it also depends on system parameters such as input inductance. The datasheet guidance is to address a wide variety of situations. If using less capacitance than the recommendation, then have options to adjust it later as needed.