LTC4013 Question

1. Datasheet says "However, during start-up and recovery conditions, the gate drive signals may be as low as 3V. Therefore, to ensure that the LTC4013 operates properly, use logic level threshold MOSFETs with a VT of about 2V or less"
We have two boards: one with CSD19538Q3A (VGS(th)=3.2V) and CSD19534Q5A (VGS(th)=2.8V), as you can see we have incorrect mosfets.
From tests seems board with CSD19534Q5A can start at 250mA charging current but has start-up charging problems at 2A.
Board with CSD19538Q3A, has problems at 250mA and 500mA charging current.
EVM board is using SiS434DN VGS(th) typ = 1.7V
Question, is that VGS(th) spec critical? what's the impact using wrong VGS(th) spec mosfet? 

2. what's LTC4013 max duty cycle?
LTC4013 specs doesn't mentioned duty cycle but it does say:
Wide Input Voltage Range: 4.5V to 60V
Wide Battery Voltage Range: 2.4V to 60V
I would usually assume that information means max Duty cycle possible is 100%, is it right?

  • 0
    •  Analog Employees 
    on Mar 18, 2020 3:37 PM 9 months ago

    Hi Julian,

    1. I would suspect this is not the issue, but with a little testing we should be able to tell. Can you get a scope plot of the BG and TG signals at the start of switching? What voltages do you see?

    2. You can calculate the max duty cycle using the min-on-time spec for BG, the non-overlap times, and your switching frequency. What is your switching frequency? The max duty cycle is not 100% but it can be pretty close.



  • Hi Zack,

    We use Vth = 3V MOS lead to start-up fail.
    So we follow datasheet suggestion to choose VTH=2V or less MOS, then, IC work normally.

    But I still had some questions...


    - When starting charger it's doing two events, a small pulse (around 2V) in bottom gate mosfet and then one-three pulses at bottom and top gate mosfets (top gate around 3V Vgs), then starts charging 1ms later doing soft-start. 

    When we use mosfet SD19538Q3A (VGS(th)=3.2V), the charger doesn't pass this stage, seems it keeps trying, we also see the infet control going down during that moment. 

    Changing to mosfet MTB020N10RV8 (VGS(th)=1.7V) then fixes this part and charger can start.

    What is the purpose of those two initial events?   What considerations need to be done to make this initial stage reliable?  What about VGS(th) dependency on temperature?

    2. Our Conditions is Vin=54V, So we need choose VDS>100V MOS.

    Bur no any VTH=2V or less MOS on this market. (VTH=2.5V what we survey lowest)

    Could you give me a detail VTH detail suggestion?

  • 0
    •  Analog Employees 
    on Mar 24, 2020 4:32 PM 9 months ago in reply to Julian Chen

    Hi Julian,

    1. Those BG pulses are normal and part of the buck's startup. The 2V recommendation is already very conservative, likely to accommodate for change over temperature. Note that the datasheet mentions a 3V minimum and then recommends 2V, so you already have the margin accounted for. You might also note that the FETs used on the DC2374B demo board have a max Vgs(th) a bit greater than 2.1V, so you should be ok.

    2. Why do you need Vds > 100V? An 80V FET should be more than enough, and you could probably get away with 60V if your rising/falling SW edges are damped enough.