I have remarked that when modifying the spice model example given in the analog website for the device that the PG pin seems to have a weird behaviour.
When I connect the Enable pin to an external pulse source, in order to enable and disable several times the device, I remark that the PG nevers pulls low when the LDO is OFF (En voltage high). It will only pull low for a short time, when the output voltage rises again from zero to is PG treshold voltage. Is that behaviour normal and will also happen in real live ? RegardsAgro
I've also checked the LTSpice model and simulate it.I got the same result as you did and it it is not the normal behavior of the PG at that condition.PG should pull low when Vout pulls low/PGFB becomes lower than 300mV (as indicated in the datasheet).
I'm communicating with the designer for the LTSpice model to be corrected.I'll get back to you once this is fixed.
I already talked to the applications engineer regarding your inquiry.And I'm correcting my statement from my previous answer.According to the apps engr, What we are getting on the simulation is correct and it is also to be expected of the behavior of PG in actual board."PG Pin is valid only when the part is ON"
Below is her exact response."The PG is valid only when the part is ON. That means when EN is below its threshold while Vin exists, and the PG voltage equals its pull up voltage. In this simulation, the PG pin is pulled to Vin. When EN is low, PG pin voltage is Vin. When EN goes above its threshold voltage, the part is ON. The PG pin is valid. It is low when Vout does not reach the programmed powergood threshold, and goes high again when Vout rises to the powergood threshold. The simulation result is exactly what the circuit performs in real tests."
Thanks and best regards,Ash