I need a circuit that detects a peak and holds the peak for 15us to be sampled by a "slow" ADC. The output should be a stable, low noise signal that does not decay within 15us, only if reset by pin. If possible, the Peak-Detector should rise as fast as possible with the signal, no long delay between Vpeak and VoutPeak.
The pulses are very sharp rising ones with a short peak and then exponentially decay. Here are the smallest and largest pulses:
Smallest pulse:Peak Value: 45mVSignal rise: ~30nsSignal fall: ~ 2 us
Largest pulse:Peak Value: 800mVSignal rise: ~50usSignal fall: ~11us
The following restrictions are given:The circuit should be possible to be powered by single supply 3.3V.The ADC reference is 2.5V Full scale, so the maximum possible gain on the largest possible pulse (1V) is 2.5If possible, negative supplies should be avoided
Is there any reference design for this or part recommendation?
the problem is, what you want implies contradicting requirements.In measurement there is something similar to heisenbergs uncertainty principle:- Either slow and precise OR fast and low accuracy.Because to be very fast needs very high Bandwidth, which results in high noise - hence low accuracy.
Also as your signal is a sharp needle, you need extremly high bandwidth, to preserve the highest signal frequencies.Otherwise your needle gets rounded off heavily.
I suppose, you use a slow ADC because of high resolution/accuracy?So please specify your accuracy requirement. That is the most stringent!What kind of ADC do you use?What is the impedance of your signal source.The problem is that to charge a storage capacitor in nanoseconds, it needs very high peak current and very high GBW of OPA.The other problem is, that you have to consider the input impedance of your ADC! You have to use an buffered ADC. Otherwise the input current and the sampling current spikes would corrupt the stored voltage.
Maybe you can deploy a peak rectifier cirquit. But the storage capacitor have to be small and maybe not sufficient for ADC.
So I think, you have to change your approach radically and use an sufficiently fast ADC (low apperture time) and add an ADC-driver stage and a peak recognition circuit to generate the sampling pulse.
The ADC i would like to use is LTC2314-14 (14bit 4.5MSPS, driven at around 1MSPS). The choice of slow adc was made because of follwoing hardware. A 1MSPS ADC can easily be controlled by standart MCU, Fast ADC usually need LVDS and FPGA Hardware. Also my signal is not a periodic one, its rather occuring spontaneous, so its not like a square wave, its pulses arriving random with much delay compared to signal lenght. For example, the maximum occuring number of pulses per second is around 2000. If the signal would be square wave, it would have a on-time of eg. 5us and off time of 495us
The signal source is a Silicon Photomultiplier, similar to a photodiode. The detector is biased with 34V and a 50Ohms resistor between cathode and GND. Between Cathode and resistor terminal, the signal is collected. This could be preamplified.About ADC, i think the current input of ADC could be solved by placing another OPAMP after the peak detector (voltage follower) or am i wrong?
For clarification i will measure the signal and upload a image
Your problem is truly "rocket science"! You underestimate that. Because you have to have experience already, to achieve best results. Additionally board layout will be really challengeing.Sorry for being unable to provide real solution.