LTC3882-1 issue

Hello,

I ran into an issue using LTC3882-1 in our custom design. We are using LTC3882-1 together with UCD7242 to generate 1.0V core Vdd for LS1046A processor. Only channel 0 of LTC3882-1 is used, channel 1 was set to be off. I am trying to figure out the source of a power glitch, where pin 7 (PWM0) was interrupted for ~140ms before recovered itself. See the below scope capture for reference. Signal 1 is pin 7 (PWM0) of LTC3882, signal 3 is 1.0V rail. 

When I read the status via I2C, channel 0 reads 0x0000 at 0x79, and channel 1 reads 0x0840 at 0x79. Also the fault log is empty at 0xEE. So the chip LTC3882 does not flag any error. All the signals around the chip are also verified to be OK. Can you please recommend where I can look at? This issue happens when our custom board draws ~2.2A on 3.3V power supply.

Thanks.

  • 0
    •  Analog Employees 
    on Mar 10, 2020 3:07 AM

    Hello

    Per the status word (0x79), channel 0 is fine. I do not see a reason for its output to momentarily go low. Here are some suggestions:

    • If 3.3V is the main supply for the rail, then make sure 3.3V is not dipping below the VIN_ON threshold. VIN_ON should be less than the minimum expected voltage during normal operation. In addition, the main input voltage should not be less than 3.0V during normal operation since this is the minimum voltage for the VINSNS pin. Also make sure the main supply is stable with low ripple.
    • Is the LTC3882-1 biased from the same 3.3V supply? If yes, then its VCC and VDD33 pins should be tied together with about 4.7uF of decoupling capacitance for the combined pins.
    • Make sure the UCD7242 gate driver bias voltage is 4.8V or higher.

    Per the status word, the OV warning bit of channel 1 is set even though this channel is off. I do not know the cause of this. If you have a schematic, then you can send it to my email address at Michael.shriver@analog.com.

    Thank you,

    Mike