I am using a LT3650-8.4 Polymer Li-Ion battery charger for two cells. The IC run well when the pull up voltage
at the status pins /SHDN, /FAULT, and /CHRG is the same as the input voltage Vin.
According to the datasheet, /FAULT and /CHRG are open collector pins, so should be possible to drive these pins
at a lower voltage, such as +3.3VDC with the purpose of interfacing to logic.
However, when these pins (all of them, or only these two with /SHDN = Vin) are driven at +3.3VDC, the current consumption
doubles after a minute or so, after it started charging the battery. This immediately leads to potentially destructive overheating
of the device.
When all the pins are pulled up at Vin, this phenomenon does not happen and the charge process completes successfully.
There is no information in the datasheet about driving this pins any voltage below Vin. Why is not possible if these are open collectors?
There is any issue at silicon level?
There should be no issue with driving these from a lower-voltage rail. I wonder if there is a sequencing issue here. There may be an ESD diode internal to the part that is sourcing current undesirably. Does your 3.3V supply come from VIN or a separate power source?
Can you try driving the pins from voltage dividers to VIN, still giving you the 3.3V logic level out, but with their supply being VIN? Even if this is just done as a test, it will help to understand the problem.
Thank you very much for your response.
The +3.3V is derived from a chain of two linear regulators (24V --> 5V and 5V --> 3.3V), whose input is Vin. The regulators have a small delay (few milliseconds) each, in their ENABLE pins, which would cause a small delay in the +3.3V relative to the rise of the +24V
Please note however, that the problem starts with a delay much larger than a few milliseconds, it can be as much as 30 seconds after the application of the +24V from the source
I carried out the test you described, connected a voltage divider 100k/30k to each pin. It doesn't do as before but the current consumption from the source still increased from 120mA to 170mA and the waveform also changed. It now has a split in the middle. The delay is not the reason of the problem.
If the pins were true open collectors as the datasheet implies, nothing of this will happen. Something seems to be wrong with these pins.
Given is too late to change the chip as the project is designed around it, actually a solution was found: The pins are driven to Vin, but at the same time, they each drive MOSFET that then interface with +3.3V. This literally provides an open drain external to the chip. Any logic can now interface with the drain of the transistors instead of the status pins directly.
Still hope to find a way to get rid of this external hardware, but the problem seems to be internal to the chip. Actually, the datasheet never shows any interface with voltages lower than Vin, so these are strange open collectors at best.
Thanks for the additional info. That's a foolproof solution, but I'll keep looking into this.
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