I'm using the LTC3351 in a product for backup power in case of power failure.
I'm using 4 x 70F supercapacitors for the backups power.
My design is based on the evaluation board with soms alternations.
Input: 18 - 25 V, Max. 5 A.
Backup voltage: 16 V.
Backup Power: about 40 W maximum.
I'm using the schematic below:
The capacitors are on a seperate PCB. I'm connecting the supercapacitors PCB with a 12 cm wire assembly.
I have made and prototype two PCB designs. My problem is that the supercapacitors don't charge if they are below 7 V. If I charge them manually to about 7 V and then connect them to the LTC3351 board they charge okay and backup is working.
If the caps are below 7 V the LTC3351 on my board tries to start charging for about a couple of ms. After that it stops and does nothing.
What can be the problem?
Hello, Sorry I could not read the schematic even if save as picture and zoomed in. To small and fuzzy. Would you include the schematic using the insert link/insert image/video/file?
Are you able to read the registers via I2C? is it possible to obtain the contents of the sys_status_reg and the monitor_status_reg? When the LTC3351 is failing to charge what is the status of the VINGD pin?
Thank you for your fast reply. Yesterday evening I discovered the problem. It was a solder problem. There was a solder bridge I missed due to assessive solder paste. I build a new prototype pcb and it works fine now. Works as expected.
Though, I have some other questions:
- Is it possible te put the LTC3351 through the reflow proces (oven) twice? For mounting SMD components on the backside or in a two phase proces.
- In the evaluation board schematic there is a 0,1 uF capacitor on the VIN pin witch is not populated. Is there any reason to use a 0,1 uF or larger capacitor on the VIN pin for stability?
- I use a ATMega164PA MCU on the system / board. I coupled the I2C interface of the LTC3351 to the ATMega164PA. On the moment I am not using this interface (I2C) but maybe I will in the future. I used 100K pullup resistors on the I2C pins. Is it good practise to set the relating pins on the ATMega164PA as output and pull them low. Or can I set the pins as input and keep both I2C pins high? What is the best way? I have no pulldown resistors and no room for them on the moment.
Thank you for your help, I really appreciate it.
Hi Rick, Thank you for the schematic and layout. This is very helpful. I wonder if resetting the VCC2P5 regulator will solve this. You can try to quickly short the VCC2P5 pin to GND when this happens for troubleshooting purposes to see if this gets you out of the situation.
The schematic looks good. I do not expect that the short 8cm cable to the caps should cause this problem. It was good that the CAPRTN was Kelvined to the caps. It would be good if CAP4 could be Kelvined also but an extra pin on the connector would be needed and this is not part of the problem. Just for reading ADC accuracy. There is a couple of concerns with the layout. The SW node, bottom and top gate are very long. These traces have fast sharp transients and can radiate noise. The top gate trace should be closely coupled with its return path the SW node. There should be a good GND path from the bottom FET back to the EPAD of the LTC3351 and C45 for the bottom gate return path. It is best to have a solid GND plane on layer 2 if possible to allow good unobstructed GND flow. It looks like there is a good SGND separate from the PGND which is good. They should be connected at a single point. We suggest from pin 11 to the EPAD. I can not tell if they are.
Do you have the DC2026 and LTC3351 software already? I do know if you have the software the DC590B can be fooled by pulling both the EESDA and EESCL lines to EEVCC (pins 11 and 9 to pin 10) with about 4.7kΩ resistor. Then the LTC3351 software can be run separately without using the QuikEval program. I expect this will work the same with the DC2026 but I never tried it.
That's all I got for now.
Thank you for you quick reply!
The SGND plane is indeed seperate of the PGND. The SGND is on the top layer. The SGND connects to pin 11 and pin 11 connects to the EPAD. On the EPAD there are 10 via's connected to all other GND / PGND layers. That is visible on the top layer. I think it is better if you download the image. I seem to have trouble on the siter with these images..
However, pin 34 RETRYB does only connect to the EPAD via a short trace. So this pin is not part of the bigger SGND plane but connects to the EPAD seperatly. This is because I had some trouble fitting the traces. I wanted to keep 6 mil spacing for production purpose and I am using 0603 components as smallest. This is because prototyping with smaller components keeps very hard. And because of the limited amount of modules being prodused right now the modules are made in house..
Okay, If I go the 6 layers instead of 4 I will be able to make layer 2 only ground layer. Now I had to make some (a lot of) compromises due to the use of only 4 layers, the placing of the connectors and so on.
We are thinking of pushing the supercaps to the same PCB and just do some alternations in the machine plating to get it to fit. Then I would be able to make the SW, TGATE en BGATE notes a lot shorter.Would this help with the problem?
Is there any other concern with the distance of the components used, like the decouple caps of the LTC3351? I will attach the BOM for you. Can you verify the MOSFETS used? Could there be any problem with the used MOSFETS in combination with the LTC3351?
Yes I do have the DC2026 kit and the LTC3351 Evaluation board and Software. So now I paralleled my 70 F supercaps with the LTC3351EVB caps and put it between our own PCB. I am trying to reproduce the same fault to be sure it is not something else causing the problem. But for now this set-up is running without any troubles.
I will try fooling the DC2026 by pulling both the EESDA and EESCL lines to EEVCC (pins 11 and 9 to pin 10) with about 4.7kΩ resistor. I will try run the LTC3351 software and get it to connect. Till now I was not ably to fool the DC2026.
Thank you for your help. Please let my know. If I made any progress from my side I will let you know. Maybe it helps other too.
I haven't been able to reproduce the error till now. I am running tests with two setups for about 80 hours non stop so I will keep testing till the problem occurs. I want to try resetting the VCAP regulator as you discribed.
I discovered that in my setup the LTC3351 keeps drawing balacing current from the caps. So the CAP3 and CAP4 balancing resistors stay hot. It seems like the LTC3351 can't get the caps to balance properly. Can this cause the problem?
Tomorrow I will experiment and try to get the evaluation module read my board. I will let you know if this is possible.
Meanwhile I am redesigning the PCB layout to adress your comments.
I discoverd a other problem with the setup. In the EMC test my board exceets the radiated emission limit around the 200 MHz frequency (30 Mhz - 1 Ghz band tested). I know these spikes are caused by the charging and balancing of the supercaps. If I disconnect the caps, the problem dissappears and the radiated emissions keep within the limits (same setup, everything else is running).
So I am considering some options.
1: Move the supercaps to the main PCB. But I have a space issue there. I can put the supercaps parrallel with the PCB and lift them about 6 mm so they are above all other components (I need to design a custom holder to attach the CAPS on the PCB then.
2: I can try to filter the EMI noise on all the supercap wires. Because I know the wires are radiating the noise. I am considering ferrite beads in series and parrallel small, low ESR caps on all the wires to the supercap stack.
With the first option I still have about 12 mm of wire for each cap in the air (because they are lifted from the board). My conserns are about the radiated emissions on these wires if I choose that option.
For option two, I don't know if ferrite beads in serie will cause any problem for the LTC3351 with the balancing? Because they will add a little resistance and induction.
What is your advise?
Best Regards,Rick Meijers
Hi Rick, Sorry for taking so long to get back to you. Are you saying R12 and R13 are getting hot? Those are the shunt resistors. Balancing starts when the caps are more than 10mV from each other. The high cap is resistive balanced with an internal 75Ω resistor. Not enough current to make the shunt resistors get hot. If any cap reaches the shunt voltad, default about 2.7V, the charger will slow down to make sure the cap does not exceed the shunt voltage and the high voltage cap will be shorted across with the 2x shunt resistors and internal FET RDSON. That will make the resistors get hot if shunting for a long time.
Can you measre the capacitor voltages and then the voltages at the LTC3351? Is it possible to check to make sure all of the capacitors are connected properly? If one is not connected then this can cause the problem.
RETRYB is a high impedance input. It does not need to connect to SGND directly in this case as long as its connected to PGND and can not couple in noise to the input. RETRYB is not floating is it? I do not see how it is connected on the layout.
What are the part numbers for the FETs? Are they logic level FETs?
MartyM said:If any cap reaches the shunt voltad, default about 2.7V, the charger will slow down to make sure the cap does not exceed the shunt voltage and the high voltage cap will be shorted across with the 2x shunt resistors and internal FET RDSON. That will make the resistors get hot if shunting for a long time.
I think this is happening. The cap voltage in the current design is 10,8 V, so 2,7 V each cap.. Later today I will measure the voltage across the casp and the voltage at the LTC3351 and let you know. I checked the connections, they are okay. I have about 5 of the same modules in test on the moment. My problem occurs about once in two weeks and it is not predictable. So it could be that in some cases, maybe because of moving the machine the connections get bad. But it is almost impossible to test this..
MartyM said:RETRYB is a high impedance input. It does not need to connect to SGND directly in this case as long as its connected to PGND and can not couple in noise to the input. RETRYB is not floating is it? I do not see how it is connected on the layout.
RETRYB is connected to the EPAD of the LTC3351 directly, so SGND. It is because there was not much room for additional traces. I am using 0603 components.
MartyM said:What are the part numbers for the FETs? Are they logic level FETs?
Texas Instruments CSD18514Q5A with a VGS(th) of 1,8 V so I don't think this is the problem? The total gate charge is about 29 nC. Is it better to look for another FET?
Because we are experiencing EMC problems while testing in the EMC room, see picture, I have decided to push the supercaps to the main PCB. The electromagnetic emissions in the red oval are radiated by the cable between the LTC PCB and the supercap PCB. Because there is not much space I dind't try it before, but because I can leave some output caps I seem to get it fit now.
So while we are testing I have been redesigned the PCB and have tried to implement all your suggestions of the first post. To prevent the LTC3351 keeps shunting I have lowered the voltage to about 9 V, I will have just enough energy for our application.
Can you give me some feedback on the new design? It is not ready yet but the part concerning the layout of the LTC3351 components is ready. I still have to make the ground planes. But Layer 2 (Mid) and Layer 4 (Bottom) are goning to be only ground layers.
FET: CSD18514Q5A (TI)
Diode D17: SD0603S040S0R2 (AVX)
Is D17 okay? it has a reverse voltage of 40 V..
Layer 1 Top
Layer 3 Mid
Thank you very much for helping out.
Thanks for sending me the layout. RetryB should be good as connected.
I did not go thru the SOA numbers or the power dissipation for the FETs in the datasheet. Other than that I think the FETs are OK.
D17 for the most part is OK. One thing to be aware of is that Schottky diodes can be leaky when hot and can charge INTVCC and DRVCC up. This did look like it had low leakage and is probably OK.
OK the schematics I have are for the new design. I do not see any issues with the new schematic.
The layout looks really good too. It looks like every recommendation we have on the layout was followed, nice job.
Having the ceramic caps close to the switcher and coupling the top gate and SW trace like already done should help with the EMC. Is the voids on the top layer going to be filled in with GND copper. I'm not an expert on EMC but look for any dead end traces that can resonate.
Thanks, Yes, I was not done yet.
I have not been able to measure the cap voltages but I will do that soon and keep you updated. I allready paid attention to possible antenna effect of dead copper ends and traces. This should be okay. But the emission was mainly radiated by the wires between the two PCB's, so I think moving the caps to the main board will solve most of that. Maybe I will put some really small (picofarats) cer. caps on the output to the caps.
If I have some more info I will post it here.