Problem with ADP3334 at initial startup

Hello Everyone,

I have used ADP3334 to execute power sequencing of adas3023. I have connected the SD pin of ADP3334 to FPGA  so that I can turn its output ON at my desired instant. Unfortunately at initial power up When FPGA is loading its program LDO ADP3334 Turns on and disturbs the power sequencing of ADAS3023. I should have used some active High LDO. But the board is prepared now. Any Help Plz ? Below is the schematic part of adp3334 and snapshot of my signals. Top waveform represents 5V-IN , Middle one is SD input connected to FPGA and 3rd is 3.3V output


Schematic and Wave form attached
[edited by: Asim Malik at 2:07 PM (GMT 0) on 16 Dec 2019]
  • 0
    •  Analog Employees 
    on Dec 16, 2019 1:33 PM


    If you have access to the PD pin on the ADAS3023 you may be able to get around this issue but forcing PD low for the duration of your power up sequence.   However, As Errgy mentioned more information would be helpful in working toward a solution.


  • I have tried a dozen combinations of power sequencing with Pd and reset also. Any time i have been able to get the activity on busy pin was the time when a pulse on pd was given after enabling the supplies. But this doesn’t always work.

  • +1
    •  Analog Employees 
    on Dec 17, 2019 9:38 PM in reply to Asim Malik


    Can you please attempt pulling up PD and RESET using weak-pull-ups to VIO so that the waveform more closely mimics the timing in figure 46 of the datasheet.    


  • Hi Sean,

    1-After setting pull up of PD and RESET to VIO device is responding well, its not latching up at least. However,  data coming out at SDO is not proportionate to the input. It seems like output is trimmed from both upper and lower ends.

    2- the same code routine is working fine on the evaluation board. Evaluation board of adas3023 is running fine. 

    3- What are the check point which can help me to dig out the problem ?

    4-  could it still be the power sequencing issue ?


  • +1
    •  Analog Employees 
    on Dec 27, 2019 3:11 PM in reply to Asim Malik


    I'm not 100% sure what you are describing with regards to the output code but I'm going to assume you mean that it is clipping and that you are getting essentially 0x7FFF and 0x8000 for some portion of the input range.   If this is not the case please do clarify with either a screen shot or other image of the output for my reference.

    Where the evaluation board is working fine with the code you provided lets assume for the moment that the digital communications are fine.

    1) Check that VDDH is at least 2.5V greater than the largest input signal into the front end of the part.  So if you are inputting 10V then the supply should be at least 12.5V for it to be linear and for the guaranteed spec you'll want it to be around 15V.

    2) Check that VSSH is at least 2.5V greater (more negative) than the most negative input signal into the front end of the part.   Again if the input swings to -10V then you'll want at least -12.5V but again for the datasheet performance VSSH should be -15V.

    3) Verify that REF1 and REF2 are shorted together otherwise the reference circuit will not work correctly.

    Measure and record the voltages at REFIN and REF1/2.

    4) Verify that AVDD and DVDD are 5.0V +/- 5%

    5) Measure and record ACAP, DCAP voltages and make sure they are properly decoupled per the datasheet.

    Let me know what you observe and if all of these values correlate with what you are seeing on the evaluation board.   Please also let me know what you are using for the configuration word and the input.

    If you are willing to share your schematic I can look that over as well.



  • Dear Sean,

    Thank you for responding. The problem was Point 3) in above reply. In my design REF1 and REF2 were not shorted. After shorting these pins I got the data perfectly fine. Thanks

  • 0
    •  Analog Employees 
    on Dec 27, 2019 3:43 PM in reply to Asim Malik

    Excellent.   Glad to be of some help.


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