Questions on BMS LTC6812/3 and active balancer LTC3300 and LT8584

Hi ADIExpert

May I have some of your suggestion on the below questions

1. In what situation or application that LTC3300-1 is more suitable than LTC3300-2 and vice versa?

2. Can LT8584 supports active balance more than 12 cells? I counld't find any reference design nor description of LT8485 that supports more than 12 cells

3.in case my customer use LTC6812//3 as a BMS with active balancer LTC3300-1/2, the GPIO[3:5] is configured to a SPI interface for communication between,

is there any spare I2C interface of LTC681x can be used for an external EEPROM that is used to store some data from LTC681x?

4. the BMS LTC681x are ISO 26262 compliant as described in the datasheet, however Could you please let me know what feature of the LTC681x that helps customer to pass the ASIL D?

my customer has highly interests on this topic and he would definitely not want to waste this feature .

thanks 

Ken

Parents
  • +1
    •  Analog Employees 
    on Dec 16, 2019 11:07 AM

    Hi Ken,

    Here are my suggestions on this

    1. The tradeoffs for these are same as for any daisy chain vs addressable communications. Some key points to consider is, with addressable communication (ltc3300-2) communication speed is better as signal does not need to propagate to all the chips. This comes with an additional BOM cost of digital isolators on each ltc3300-1 and different HW configuration (address pins) for each board in a system.

    2. There are 2 ways of doing the active cell balancing, one at the stack level when modular battery architecture is considered and the other at the cell level, if it is used in stack level balancing then 12 cells is an appropriate fit (note voltage limit of this IC is 50V). If it is on a cell basis then it can be cascaded to any cells as each cell uses one LTC8584. The only thing to consider here is the voltage limit of the IC wrt to it's reference ground. You can have a 96s system with 8 stacks of 12 cells, each with 12 LTC8584.

    3.  There is only one auxiliary communication channel on 6812/13 which can be configured as SPI or I2C. But you can tackle this issue in two ways

    • Use LTC3300-1 controlled by the master MCU and communicate through all the ICs serially. This will free SPI pins on all the 681x chips. You can I2C to WR/RD EEPROM then. 
    • Use SPI based EEPROM and use one of the GPIO as CS.

    4. To make a system ASIL D you need to have  redundant Hardware or Implementation of safety mechanisms in the software like cell open wire check, MUXfail check, redundant ADC measurements, ADC self-tests, Redundant Digital filter check, data register checks, internal die voltage and temperature check, reversible iso-SPI etc. performing these checks in a fixed time interval will help you get the ASIL D certified system. Since it is a system requirement I will be needing more information about your system to confirm on this.

Reply
  • +1
    •  Analog Employees 
    on Dec 16, 2019 11:07 AM

    Hi Ken,

    Here are my suggestions on this

    1. The tradeoffs for these are same as for any daisy chain vs addressable communications. Some key points to consider is, with addressable communication (ltc3300-2) communication speed is better as signal does not need to propagate to all the chips. This comes with an additional BOM cost of digital isolators on each ltc3300-1 and different HW configuration (address pins) for each board in a system.

    2. There are 2 ways of doing the active cell balancing, one at the stack level when modular battery architecture is considered and the other at the cell level, if it is used in stack level balancing then 12 cells is an appropriate fit (note voltage limit of this IC is 50V). If it is on a cell basis then it can be cascaded to any cells as each cell uses one LTC8584. The only thing to consider here is the voltage limit of the IC wrt to it's reference ground. You can have a 96s system with 8 stacks of 12 cells, each with 12 LTC8584.

    3.  There is only one auxiliary communication channel on 6812/13 which can be configured as SPI or I2C. But you can tackle this issue in two ways

    • Use LTC3300-1 controlled by the master MCU and communicate through all the ICs serially. This will free SPI pins on all the 681x chips. You can I2C to WR/RD EEPROM then. 
    • Use SPI based EEPROM and use one of the GPIO as CS.

    4. To make a system ASIL D you need to have  redundant Hardware or Implementation of safety mechanisms in the software like cell open wire check, MUXfail check, redundant ADC measurements, ADC self-tests, Redundant Digital filter check, data register checks, internal die voltage and temperature check, reversible iso-SPI etc. performing these checks in a fixed time interval will help you get the ASIL D certified system. Since it is a system requirement I will be needing more information about your system to confirm on this.

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