T2P, Power Demotion, SG, Ideal diode bridge in DC2476A-A

To whom may it concern.

Hi I'm HS.

I have DC2476A-A and want to use T2P as type indicator via LEDs, which means I want to use 3 LEDs so that they indicate 4 states: af, at, bt(around 61W), bt(around 71W)

I set the output as 28V.

If I attach the LEDs to the secondary part of octo-coupler, LEDs will be oscillating from V_OUT=28V to 0V so it may make users frowned upon or seem to be stagnant since Pin T2P throw pulses out to octo-coupler at 976Hz.

So my question is...

1. What would be the most effective way to indicate 4 states using LEDs?

2. Is there any specific action when PD is demoted so that you can tell it is demoted or just normal operation.

ex) Datasheet said, 50% 976hz pulse means 51W --> Class 6.

How do you know if it's normal operation(class 6 by itself) or it is demoted?

3.

3-1. I want to change the voltage level of the T2P pulse cuz it's too high(Since V_OUT=28V) to connect to LEDs

Would it be ok if I pull-up to other voltage values, somewhat lower than V_OUT(=24V)?

Or How can I lower the voltage value in addition to connecting resistors in series with pull-up resistors?

3-2. I think i may attach LC filter to T2P so that it alters pulse into a smoothly-filtered continuous voltage waveform, DC. 3 comparators which are made of op-amps will be placed next to the LC filter. I hope the output of comparators is around 1.8V. I think I draw 1.8V from somewhere, idk..maybe voltage regulator from 7805 or something, and connect it to VDD of comparator.

Do you think it's a good idea to discern the state of PD(af,at,bt) and send this data/signal to end- device??

3-2-2. Comparator's VCC and V_REFs will be given/divided by V_OUT. V_REF will be referenced from V_OUT via 5.1V Zener Diode. Do you think it's a good way to get VCC from secondary area? 

4.

4-1. What's the purpose of R13, C17 on the primary side of T3 and C20, D13, R18, R15 on the secondary side?

4-2. Reference schematic put  zener diode, D17(PMEG1020EA) at Pin PG , but no zener at Pin SG. What's the difference??

4-3. Reference schematic put gate driver at secondary power MOSFET but nothing at primary power MOSFET. What's the difference??

4-4 Why does gate driver need Transformer(T3)?, Why didn't reference design connect gate driver to Pin SG directly??

5. In reference schematic, Output filter has R35(Opt). What effect can we expect if we insert this R35? Any voltage drop? Higher filter performance??

6. In reference schematic, R5(8.2Ohm) is connected to Pin VPORT in LT4295. What's the purpose of this R5?

7. This is the screenshot of PoE ideal MOSFET Diode Bridge using LT4321 in DC2476A-A

What's the purpose of R28, D2, D3 and C11??

8. Layout.

I couldn't find any information/tips for layout of DC2476A-A.

Is there anything that i have to know and take care of when it comes to layout??

I think you guys use 6 layers PCB.

What's the impedance of pcb and what width should i use for line and data??

Thank you for your hard work and I appreciate it a lot

Hope you have a good day



Added layout
[edited by: feelyoursoul at 12:26 AM (GMT 0) on 26 Nov 2019]
Parents
  • +1
    •  Analog Employees 
    on Nov 26, 2019 7:53 PM

    1. The T2P pin uses duty-cycle to encode the physical layer classification result, which is how much power the PD has been allocated. This means you only need to use a single opto-coupler to send this information across the isolation barrier. A microprocessor is the simplest way to decode this information. This only requires a single digital input and a couple lines of code.

    2. You know if the PD is demoted by comparing the PD’s Requested Class (i.e. what resistors are installed at the CLASS and CLASS++ pins) and the T2P signal. Requested Class is determined when you build the PD, it does not change. If you see T2P with a 50% 976Hz pulse, the PD has been demoted if it is Class 7 or Class 8, but it has received full power if it’s Class 5 or Class 6. For example, see Table 5 in the datasheet. A Class 6 PD has four T2P states. They correlate with Demoted to 13W, Demoted to 25.5W, Received Requested 51W, and operating with Auxiliary Power.

    3-1. Yes, you can use a lower voltage to drive the opto-coupler’s collector. 24V is used on this board because that is the output voltage. The opto-coupler supply can easily be lower; 3.3V and 5V are commonly used. I recommend using a resistor / BJT / Zener regulator for a quick and cheap low voltage, low current supply. An linear regulator is another option.

    3-2. The downstream circuitry should know the T2P result, so it can reduce the load if the PD has been demoted. If a PD doesn’t implement demotion it may be disconnected by the PSE when it draws too much power. As I mentioned earlier, it is quite trivial for any microprocessor to detect a digital duty cycle. An averaged (LC filtered) T2P signal can also be measured with an ADC. Using comparators is another good option. You could also use a window comparator to detect if the average T2P signal is at 50%, etc.

    3-2-2. I don’t see the Zener in the schematic you shared. Please see the earlier comment about using a Zener and BJT to generate a low voltage bias rail. I also recommend you simulate your LC filter and comparator circuit using LTSpice.

    4-1. These components form an undamped L-C circuit for the isolated secondary-side gate driver signal. I do not recommend changing these values.

    4-2. This is a Schottky diode, not zener. I recommend BAT54WS for new designs. The SG pin does not need a diode.

    4-3. A gate driver is needed on the secondary because the gate drive signal should be refreshed after crossing the isolation barrier.

    4-4. The secondary-side needs to be isolated per IEEE, to 1500VRMS.

    5. This resistor optionally damps the output filter, as the inductor affects the control loop. This resistor would allow us to bypass the filter or modify the filter response for different designs. You can ignore it for your design.

    6. This resistor is optional and improves performance.

    7. C11 locally biases the LT4321, D2 provides protection, R28 allows you to optionally use /EN and D3 enables the bridge after classification.

    8. Please use the DC2476A-A as a guideline for the layout. Follow the standard rules for a flyback or isolated converter layout. DC2476A-A is a 6-layer board, but the design could modified for a 4-layer board, perhaps even a two layer with some care. Please keep the data + power traces as short as possible and size correctly for current capacity. These are the traces between the RJ-45 and ethernet transformer. The data traces that come from the ethernet transformer are differential pairs. Each pair should have a differential characteristic impedance of 100 Ohms. I recommend you follow the guidelines provided by your PHY manufacturer.

    Best Regards,

    Eric

Reply
  • +1
    •  Analog Employees 
    on Nov 26, 2019 7:53 PM

    1. The T2P pin uses duty-cycle to encode the physical layer classification result, which is how much power the PD has been allocated. This means you only need to use a single opto-coupler to send this information across the isolation barrier. A microprocessor is the simplest way to decode this information. This only requires a single digital input and a couple lines of code.

    2. You know if the PD is demoted by comparing the PD’s Requested Class (i.e. what resistors are installed at the CLASS and CLASS++ pins) and the T2P signal. Requested Class is determined when you build the PD, it does not change. If you see T2P with a 50% 976Hz pulse, the PD has been demoted if it is Class 7 or Class 8, but it has received full power if it’s Class 5 or Class 6. For example, see Table 5 in the datasheet. A Class 6 PD has four T2P states. They correlate with Demoted to 13W, Demoted to 25.5W, Received Requested 51W, and operating with Auxiliary Power.

    3-1. Yes, you can use a lower voltage to drive the opto-coupler’s collector. 24V is used on this board because that is the output voltage. The opto-coupler supply can easily be lower; 3.3V and 5V are commonly used. I recommend using a resistor / BJT / Zener regulator for a quick and cheap low voltage, low current supply. An linear regulator is another option.

    3-2. The downstream circuitry should know the T2P result, so it can reduce the load if the PD has been demoted. If a PD doesn’t implement demotion it may be disconnected by the PSE when it draws too much power. As I mentioned earlier, it is quite trivial for any microprocessor to detect a digital duty cycle. An averaged (LC filtered) T2P signal can also be measured with an ADC. Using comparators is another good option. You could also use a window comparator to detect if the average T2P signal is at 50%, etc.

    3-2-2. I don’t see the Zener in the schematic you shared. Please see the earlier comment about using a Zener and BJT to generate a low voltage bias rail. I also recommend you simulate your LC filter and comparator circuit using LTSpice.

    4-1. These components form an undamped L-C circuit for the isolated secondary-side gate driver signal. I do not recommend changing these values.

    4-2. This is a Schottky diode, not zener. I recommend BAT54WS for new designs. The SG pin does not need a diode.

    4-3. A gate driver is needed on the secondary because the gate drive signal should be refreshed after crossing the isolation barrier.

    4-4. The secondary-side needs to be isolated per IEEE, to 1500VRMS.

    5. This resistor optionally damps the output filter, as the inductor affects the control loop. This resistor would allow us to bypass the filter or modify the filter response for different designs. You can ignore it for your design.

    6. This resistor is optional and improves performance.

    7. C11 locally biases the LT4321, D2 provides protection, R28 allows you to optionally use /EN and D3 enables the bridge after classification.

    8. Please use the DC2476A-A as a guideline for the layout. Follow the standard rules for a flyback or isolated converter layout. DC2476A-A is a 6-layer board, but the design could modified for a 4-layer board, perhaps even a two layer with some care. Please keep the data + power traces as short as possible and size correctly for current capacity. These are the traces between the RJ-45 and ethernet transformer. The data traces that come from the ethernet transformer are differential pairs. Each pair should have a differential characteristic impedance of 100 Ohms. I recommend you follow the guidelines provided by your PHY manufacturer.

    Best Regards,

    Eric

Children