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LT3753 PMOS rating @ hard stop case

Hi ADI EXpert

I have a question relates to the demag PMOS of LT3753

My customer has an application to convert 18~32V to 24V/5.5A by LT3753

He Showed me that the PMOS Vds is over the rating when hard-stop occurred (OUT, AOUT stop switching in a very short-time) at very light load condition.

so I ran a simulation based on the LT3753 model in the LTspice example folder.

and the simulation is exacly similar to what I saw from my customer's issue(Note: the simulation didn't base on my customer's spec however similar phenomenon can be observed)

please see the waveform below

1. First, I ran the simulation until Vout is stable to 5V @ (around 4ms)

2. I add an Discharge current source 0.9mA @ SS1 to simulate the hard stop

As we can see from the waveform, the NMOS(M1)_G and PMOS(M4)_G stop switching almost immediately at 4.5ms.

however,  some oscillation still can be seen at the NMOS_Drain after both switches stopped. and the PMOS(M4) drain waveform looked like the AC couple voltage of the NMOS(M1) through C11

As we can see in the simulation, There is indeed a  negative peak voltage measured at the PMOS_D which may over the BVDSS 

so, here are my questions about the phenomenon

1. Will this negative peak damage the PMOS if the voltage is over the BVDSS of the PMOS, considering it's an AC coupled signal without DC current path?

2. if it's yes from Q1, is there any method we can use to clamp the NMOS_drain voltage? 

3. May I have some of your experience sharing with me since I don't really figure out how the oscillation was occurred after two switches stop switching? did it cause by the Lmag and the Cclamp??

I attached the simulation for your reference3753_Ken.rar

Any suggestion would be very appreciated 

thanks

Ken



change Q3 description
[edited by: Kencheng at 4:29 PM (GMT 0) on 24 Nov 2019]