First off I want to say that this is a really interesting part, and the combined system using the 4120 to control the charging of a battery without the use of a digital communication channel is innovative.
I have the demo board for the LTC4125, and am working on adapting this to our magnetic system and application, with an eye towards adapting it further for some innovative ideas. But I am struggling to understand some things that are in the datasheet and about the part that I hope I can get some help with from here.
Regarding the PTH1 and PTH2 pins, looking at the 4125 rev f datasheet on page 8, the block diagram shows these pins connecting to separate DACs, with some form of pulse width modulator connected between the two that feeds back to the logic circuits. But on the demo board, these two pins are shorted together. How does this not cause the two DACs to fight each other, unless they are set to the same output? And even then, they will never be exactly the same so some current must flow between the two? On page 17, there is a test procedure to determine the maximum tank voltage, where on step 2 it instructs me to short these two pins together. Why? How does the part's function change when these pins are left floating, versus when they are connected together? In several places on the datasheet, there are graphs that have "Vpth1=Vpth2", does this mean the pins were shorted at that time, or that they just naturally have the same DAC output at that time? To further confuse me, figure 13 has a graph that has labeled one of the traces "Vpth1/Vpth2". Does this label mean that that Vpth1 is stepping higher than Vpth2, or that they are both rising in lockstep, or the pins are shorted together?
The pin description tells me that PTH1 is related to the PW on SW1, and PTH2 for SW2. But this also is not clear to me, since SW1 is actually two FETs, A&B, and SW2 is C&D. In operation, either C and A are on, or D and B are on, or all are off? Or does the system sometimes turn on C and B when the PW is less than 50%? Does PTH1 represent the duty cycle on time for FETs C&A, and PTH2 the duty cycle on time for D&B?
Is it possible to control the duty cycle of the bridge FETs using these PTH pins as inputs? Can you operate the bridge externally using these pins as inputs to control the two bridge halves asymmetrically i.e. with different PWs?
Thanks for the help - Brian