First off I want to say that this is a really interesting part, and the combined system using the 4120 to control the charging of a battery without the use of a digital communication channel is innovative.
I have the demo board for the LTC4125, and am working on adapting this to our magnetic system and application, with an eye towards adapting it further for some innovative ideas. But I am struggling to understand some things that are in the datasheet and about the part that I hope I can get some help with from here.
Regarding the PTH1 and PTH2 pins, looking at the 4125 rev f datasheet on page 8, the block diagram shows these pins connecting to separate DACs, with some form of pulse width modulator connected between the two that feeds back to the logic circuits. But on the demo board, these two pins are shorted together. How does this not cause the two DACs to fight each other, unless they are set to the same output? And even then, they will never be exactly the same so some current must flow between the two? On page 17, there is a test procedure to determine the maximum tank voltage, where on step 2 it instructs me to short these two pins together. Why? How does the part's function change when these pins are left floating, versus when they are connected together? In several places on the datasheet, there are graphs that have "Vpth1=Vpth2", does this mean the pins were shorted at that time, or that they just naturally have the same DAC output at that time? To further confuse me, figure 13 has a graph that has labeled one of the traces "Vpth1/Vpth2". Does this label mean that that Vpth1 is stepping higher than Vpth2, or that they are both rising in lockstep, or the pins are shorted together?
The pin description tells me that PTH1 is related to the PW on SW1, and PTH2 for SW2. But this also is not clear to me, since SW1 is actually two FETs, A&B, and SW2 is C&D. In operation, either C and A are on, or D and B are on, or all are off? Or does the system sometimes turn on C and B when the PW is less than 50%? Does PTH1 represent the duty cycle on time for FETs C&A, and PTH2 the duty cycle on time for D&B?
Is it possible to control the duty cycle of the bridge FETs using these PTH pins as inputs? Can you operate the bridge externally using these pins as inputs to control the two bridge halves asymmetrically i.e. with different PWs?
Thanks for the help - Brian
Are you able to help the customer, please.
Thanks for bringing up this interesting topic of LTC4125. These two pins does expand the potential of the LTC4125 by allowing control over the duty cycle of the two bridges while still maintain the AutoResonant feature.
The DACs on PTH1 and PTH2 have an internal 100k resistor at their outputs. So when the output of the DACs are slightly different, with the 100k resistors, only small current is flowing through the resistors. Plus, these two DACs are set to have the same output, so the difference can only be really small. As a result, shorting PTH1 and PTH2 together will not hurt the DACs. It only guarantee that the two bridges are at exactly the same duty cycle. By the way, the duty cycle is depended on the voltage on the each PTH pin, instead of the output of the DAC.
On page 17, shorting PTH pins together and sweep the VPTH is just to make sure both PTH pins are at the same level when driving external or internal. This is the most common use case in the applications. If these pins are not shorted together and you are driving theses two pins with different voltage externally, the result can be different from when driving it internally in the search period. As a mentioned before, when these pins are driven internally with the DACs, they should have almost the same value, even if they are not connected together.
Figure 13 the trace "Vpth1/Vpth2" means PTH1 voltage or PTH2 voltage, instead of dividing PTH1 with PTH2. Sorry for the confusion.
You are correct that PTH1 controls A&B, while PTH2 controls C&D. When A is on, B is off and when B is on, A is off, which is also the same for C&D. The PTH1 duty cycle is defined by the turn on period of the top switch A, comparing the switching period. The start of the switching period is defined as the current changing direction in SW1 from flowing in to flowing out. The same idea for PTH2 and SW2. The duty cycle of PTH1 and PTH2 are locked to below 50%, so switch A and C will not be on at the same time. Switch B and C can be on at the same time, and the resonant tank is just circulating its current via these two switches. Figure 3 and figure 4 should help you understand this process.
The PTH pins can be used as input if you want to command the duty cycle externally. These two bridges can be controlled separately to create different duty cycle on the two hald-bridges. In fact, you can short PTH2 to ground to make D shut off all the time and C turn on all the time, and in this way, you make LTC4125 a half bridge converter. When controlling the PTH pins externally, please make sure they do not exceed the voltage limits on these two pins. Also, please take into the account of the 100k output resistor for the internal D/A. When driving it externally, it is recommended to fake a exit condition to actively disable the search feature. When I usually do is to connect a 1V regulator (ADR510) at IMON pin, so whenever there is current flowing between IS+ and IS-, the exit condition is triggered, and the DAC output is low as the search exits at the beginning.
We are also working on a another LTC4125 applications design that controls the PTH pins externally. An article of this new application idea will be published later this year or early next year.
I look forward to your new idea with the parts. If you have any further questions, please let me know.
Thank you Wenwei for your detailed response. I believe that you have cleared up all of my misunderstanding with this IC and I can get on with my work.
One item that I believe is in error in your response is "...so switch A and C will not be on at the same time." I believe this statement should read "...so switch A and D will not be on at the same time." A and C should be on at the same time in order to inject energy into the resonant circuit. Just being a bit pedantic so that someone reading this later may benefit.
I look forward to your new paper on the new application idea.
Thanks Brian for correcting my mistake. It is indeed the two upper PFETs, A and D, may not conduct at the same time as the duty cycle is less than 50%.