ADN8831 Output Voltage Different from Datasheet - Outputs diverse before linear side saturates.

I am having a problem with the high-side (linear-side) FET overheating.  Some heating is normal in low current when the linear FET is not saturated and the voltage on that side of the TEC is not 5V or 0V.  My TEC is Laird SH14-15-06.  Its V-I curve is similar to a 0.25 ohm resistor. So 1V results in 4A.

Here is the expected voltage output vs VOUT2 according Page 17 of the ADN8831 datasheet.

I calculated my FETs' expected temperature rise vs TEC Current

The problem is the low side (switching side) does not rise fast enough with respect to VOUT2, so the linear side transistor stays in linear (non-saturated) mode for higher TEC voltages.  Here is the measured TEC Voltage vs VOUT2:

Here it is in chart format:

 OUT2 V[High] (Linear) V[Low] (Swiching) I[TEC] V[TEC] Transistor Pwr 1.255 1.38 1.31 0.22 0.07 0.79 1.245 1.83 1.69 0.35 0.14 1.09 1.241 2.04 1.87 0.48 0.17 1.40 1.236 2.31 2.11 0.7 0.2 1.85 1.225 2.86 2.5 1.5 0.36 3.14 1.217 3.3 2.82 1.5 0.48 2.48 1.208 3.78 3.14 1.88 0.64 2.20 1.199 4.11 3.28 2.22 0.83 1.86 1.189 4.63 3.65 2.69 0.98 0.86 1.176 4.94 3.82 3.02 1.12 0.03

The worst case is when OUT2 = 1.225V.  The transistor dissipates 3.14W.

Part of my issue is the TEC's low V/I ratio ("resistance"), but this would not be a problem if the TEC controller provided the voltage outputs on Page 17 of the datasheet.

Might a larger inductor help?  Can someone knowledgeable about the workings of ADN8831 suggest why the voltage outputs are diverging so far before the linear side ("high-side") is saturated?

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• Hi ,

Thank you for posting your questions here in engineerzone. I am an applications engineer supporting the ADN883x products.

With regards to your inquiry, here below are response:

in linear (non-saturated) mode for higher TEC voltages.  Here is the measured TEC Voltage vs VOUT2:

Please know that this curve is valid only during open-loop setting, without load connected between LFB and SFB.

With a load connected across the LFB and SFB is a different scenario and the graph showing the SFB output is now not valid.

With a TEC connected, the SFB out will now depend on the following factors:

1. TEC resistance.
2. Level of the current limit set (ILIM).

Let’s consider the following condition:

In your case, let us say OUT2 is around 1.15V; ILIM is set to 1.25A.

With this condition, computing for the outputs as per page 17 will be:

LFB = 5V (clamped to rail)

SFB = 4.5V ; giving TEC voltage of 0.5V.

Having a TEC resistance of 0.25ohms, and TEC voltage of 0.5V will ideally give ITEC (current across the TEC) = 2A.

Given that ILIM is set to 1.25A thus not allowing 2A to flow across the TEC, the SFB will adjust accordingly.

The LFB output will be the priority, then the SFB will adjust to comply. You can notice it on the formula for computing the LFB and SFB output.

SFB is dependent on LFB, while LFB is dependent on VB which is a defined value.

This can also answer your observation on why the switching side does not rise fast enough with respect to VOUT2.

To clear this out, we need to confirm on the following:

1. What is the current limit setting of your circuit?
2. If it is ok with you, can you share to us your schematic so we can help you?

On this part there are things that we would like to clarify:

Here it is in chart format:

 OUT2 V[High] (Linear) V[Low] (Swiching) I[TEC] V[TEC] Transistor Pwr 1.255 1.38 1.31 0.22 0.07 0.79 1.245 1.83 1.69 0.35 0.14 1.09 1.241 2.04 1.87 0.48 0.17 1.40 1.236 2.31 2.11 0.7 0.2 1.85 1.225 2.86 2.5 1.5 0.36 3.14 1.217 3.3 2.82 1.5 0.48 2.48 1.208 3.78 3.14 1.88 0.64 2.20 1.199 4.11 3.28 2.22 0.83 1.86 1.189 4.63 3.65 2.69 0.98 0.86 1.176 4.94 3.82 3.02 1.12 0.03

The worst case is when OUT2 = 1.225V.  The transistor dissipates 3.14W.

• We would like to know on how the ITEC was computed. Is it by VTEC divided by the TEC resistance?
• Same thing with transistor power dissipation computation and how it was computed.

We have here sample computation that based on your values.

But in here, we got ITEC by VTEC divided by the TEC resistance (assumed to be 0.25ohms).

Based on the given circuit VDS of the PMOSFET can be determined.

By KVL:

VDD – VDS – ITEC*Rsense – VHIGH = 0

Therefore,

Consider the given values

VDD = 5V ; ITEC = 1.5A ; Rsense = 0.02 ; VHIGH = 2.86V

VDS = VDD – (ITEC*Rsense + VHIGH)

VDS = 5V – (1.5*0.02 + 2.86)

VDS = 2.11V

Power Dissipation of transistor on this condition will be:

Pdiss = VDS*ITEC

Pdiss = 2.111*1.44

Pdiss = 3.04W

Having these values, we can now predict the Temp Rise by multiplying it to thermal resistance.

TFET = 3.04*52 = ~150degC

Thank you and best regards!

• If it is ok with you, can you share to us your schematic so we can help you?

• Hi ,

Do you know any tricks I can do with VLIM and ILIM to get the part to saturate the linear transistor at lower currents?

As we can see, the power dissipation is very high at the active region of the FET (in between the fully-on and the fully-off of the switch). The blue curve is the transistor power dissipation versus the ITEC. As of now, what we have in mind to help you on what you can do for the part not to heat so much is to intentionally make it not to operate at the region where the power is maximum.

TEC+ and TEC- versus OUT2

Projecting the Power Dissipation on the Output:

We know that OUT2 controls TEC+ and TEC-. Therefore with faster response of OUT2, the less time for the transistor to operate in the region of highest power dissipation (the slope of the TEC+ and TEC- will become steep). That can be achieved by increasing the gain of chopper2. You can see it based on the formula in the datasheet.

Since the compensation is internal, we need to be cautious in adjusting it since it may lead to oscillation and instability.

Another thing is that you might want to use heatsink on your FET thus minimizing the heat and reduce thermal stress on it.

• Hi CJ,

Apologies for the late response. However, we cannot change the TEC+ versus OUT2 relationship as it is internal. You're right, only making it OUT2 faster.

• Hi CJ,

Hope everything is doing great!

We did a simulation similar to your condition to compute for the FETs' power dissipation. Here it is below.

The curve is the FET's power dissipation vs. OUT2 voltage and on the right is the table of values of LDR, SFB, ITEC at given OUT2 voltage values.

The maximum power dissipation we got is only around 0.7044W for PFET and 0.8532W for the NFET.

We also computed for the temperature change at the given power dissipation using the datasheet values of the FET you are using. The max temperature change is around ~45degC.

If you have some questions and you want us to discuss, kindly send me an email on noel.tenorio@analog.com

Thank you and best regards,

Noel

• Hi CJ,

Hope everything is doing great!

We did a simulation similar to your condition to compute for the FETs' power dissipation. Here it is below.

The curve is the FET's power dissipation vs. OUT2 voltage and on the right is the table of values of LDR, SFB, ITEC at given OUT2 voltage values.

The maximum power dissipation we got is only around 0.7044W for PFET and 0.8532W for the NFET.

We also computed for the temperature change at the given power dissipation using the datasheet values of the FET you are using. The max temperature change is around ~45degC.

If you have some questions and you want us to discuss, kindly send me an email on noel.tenorio@analog.com

Thank you and best regards,

Noel

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