Can I use an external pullup to force the TIMER pin high (to VCAP) and thus cause a latching turn-off of the ADM1275-2? I'd like to do this to implement an overvoltage protection on a secondary voltage that is derived from its output. Please comment if this is OK and works, and if there is anything known about the propagation time from V(TIMER) > VTIMERH to GATE being pulled low?
Unfortunately, your suggestion won't work. The TIMER pin is active when the FET is in current limit, and won't detect the voltage when the FET is fully enhanced. Pulling the OV pin to VCAP will turn off the FET, but will not latch automatically. One possible solution is to artificially induce an overcurrent fault by applying a weak pulldown to the SENSE- pin of the IC. The 10ohm resistors will drop some voltage, making the IC sense a large differential voltage that seems like OC. Then you should be able to take advantage of the latching behavior of the ADM1275.
Thanks for the fast response on this. Your proposed way to do it sounds indeed better than my initial guess. Can you confirm here, if I make >50 mV artificial SENSE+/- differential this will activate the 'severe overcurrent' fast trip feature and shut down promptly (and latching) without waiting for the timer? That will be essential for OVP function, of course. Also let ask: The datasheet note "VISET = 1.0 V; VFLB > 1.1 V; VSS ≥ 2 V" on the severe overcurrent threshold spec makes me wonder how does this interact with soft start? One scenario for an overvoltage event is of course failure of the secondary voltage converter circuit and this might happen right away on power-on and I'd want the OVP detection to kill the power asap, even if the circuit is still in a soft-start cycle. Can you confirm it would work like that?
Many thanks, and I hope to hear about these details and then will design this in. It is very nice part. BTW I will use LTC1696 for the OV detection, seems a good plan.
Yes, if you exceed the severe overcurrent limit (nominally 50mV) during normal operation then the SOC response will immediately activate and the timer will not run. During startup, however, this severe overcurrent mechanism doesn't come into play, since it is assumed that the output ramp moves the voltage slowly, and the active current control loop remains in effect. This is especially true as the soft start feature keeps a tight lid on the magnitude of the current. Starting into a dead short will result in the output not ramping and the gate actively limited by the current limit. All of that to say that the timer will run in that case (startup overcurrent), and your OVP scheme won't be fast while the hotswap is starting. Probably not what you want.
Since you are using the LTC1696, which has its own latching feature, why not use it to pull down ENABLE on the ADM1275? Disabling the ADM1275 will immediately turn off the FET, and the LTC1696 will latch off until you reset it by toggling its ENABLE. The advantage here is that you will have independent, unambiguous control over when and how the ADM1275 turns on and off.
Ok, understood. Actually I am committed to using ADM1275-2 so I don't have ENABLE pin but I do have the UV pin and could use it in the same way. But I see that only activates the "slow" gate pulldown (10 mA). What by the way would result from taking ENABLE low on ADM1275-3 - is it again the 10 mA gate pulldown or the high current pulldown? My FET (PSMN1R4-30YLD) will have Qg about 55 nC so this will take about 5.5 us for turn-off - maybe OK but 10x faster would probably be better.
Perhaps I have to just externally pull the gate down - is that OK? I don't see anything in ADM1275 datasheet that looks like incompatible with doing that but would like to know what you think about it.
This whole OVP functionality is sort of an afterthought which I wanted to add to a near-finished design using the ADM1275-2, to provide an extra level of protection for an _expensive_ board.
Unfortunately today (after the earlier message) after a closer look at the LTC1696 datasheet I think I have concluded I cannot use it, the voltage tolerance is too loose. I would be wanting to set an OVP for a Xilinx FPGA 1.0 V core voltage which has an absolute max rating of 1.1 V, and this has to work over -40 deg C to +85 deg C. The datasheet offers only that the reference voltage is max 0.907 V, min 0.853 V which offers no higher than 1.034 V for the minimum trip threshold which is not high enough. If I will do this OVP circuit I guess I will have to use some higher precision reference and comparators. I may give up on it all if there is no simple circuit for this, but I am still mulling it over.
Any further thoughts and advice will certainly be appreciated! Thanks, sincerely,
True, the UV pin will activate the normal pulldown current, which should move the gate reasonably quickly, but keep in mind that the primary force moving the voltage on the bulk capacitors is NOT the hotswap turning off, it is the load (your switching regulator and expensive FPGA) pulling current to ground. I doubt that your FPGA is going to discharge the bulk capacitors in 6us. This means that the hotswap will be plenty fast, and the real problem is yanking all of that stored energy out of the bulk caps before it reaches the FPGA. This is a completely different circuit, composed of a supervisor and a giant discharge FET. Not a simple affair!
I would recommend that you try using a supply supervisor, like the LTC2933 or LTC2936, which have the precision reference and comparators built in (1% accurate), plus they are programmable so offer flexibility. They were made for your application. You could use one of the open drain outputs to pull down on the ADM1275's UV pin.
The following application note gives a few pointers on the topic of powering FPGAs. Maybe you'll find it interesting.
Thanks, that is an interesting suggested part. (And an interesting and useful appnote.)
But the response time of LTC2933 is perhaps slower than we should have for overvoltage protection, I worry. It sounds like even with 80 mV overdrive it takes typically 25 us to make an output to use to pulldown the UV pin. I guess I am a little worried about this, although I don't really know what time scale is needed in an OVP circuit for FPGA core. (Something to add in next appnote?)
Also I did not mention before but I think for our application I better use OVP thresholds controlled by resistors not EEPROM, there may be a higher than normal radiation upset probability in our applications. (This thing will be flown on a high altitude research balloon. We must certainly not have an erroneously lowered OVP threshold due to a radiation upset.)
Would you be able to recommend a similar supervisor (ideally for >=3 supplies) with <2% accuracy over -40 to +85 with faster response and fixed (resistor-programmed) thresholds? If there is such that would be nice indeed.
Also, what do you think about externally pulling down the gate of FET that is normally under the control of ADM1275? This should be OK, right? (I am asking only that it would not damage the ADM1275.)
Thanks for continuing the conversation, sorry I am not quite converged on what to do yet but I appreciate your patience.
I don't speak for Xilinx, but I suspect that the timescale for damage to the FPGA depends a lot on how high the voltage spikes up during the event. For a 12V overvoltage, like when the top FET of your switching regulator shorts out, all bets are off. Your best protection against such an event would be to place two or three series connected forward-biased heavy-duty diodes (0.6V+0.6V=1.2-ish V) across your 1V supply near the FPGA. These will not conduct when the 1V supply is normal, but will clamp if the voltage tries to spike and they will dissipate as much energy as possible before it can damage the FPGA. For lower voltages the damaging effects will take longer. I expect that the ESD structures inside of the FPGA will kick-in and dissipate as much energy as they can before the FPGA logic devices themselves are damaged, but I don't know at what voltage they fire up. For voltages less than the ESD clamps the effects tend to be long term oxide aging inside of the FPGA, and not a big concern for a one-time emergency. Again, though, I don't speak for Xilinx.
My expectation is that the afore mentioned healthy diode clamp will do more to protect the FPGA than a faster supervisory comparator. Most supply supervisors, including such resistor-programmable ones as the LTC2962, have deliberately slower (10s of microseconds) comparators to prevent glitching behavior (the glitching behavior can be maddeningly difficult to debug, and really helps nothing). As I mentioned before, shutting down the hotswap is only the first step in the process of protecting the FPGA. You still have huge banks of +12V charged capacitors to contend with even if the ADM1275 turns off instantly.
As for externally pulling down the FET gate, there are some potential problems here. The ADM1275 expects that it is in sole control of the gate, and it applies controlled currents as necessary. In the past I have done experiments pulling down the gate through a low impedance that caused internal damage to the hotswap controller (uncontrolled currents flowing through internal diodes in the IC). Since then I always pull very gently, through a 100k resistor. I think you should avoid yanking down on the gate pin.
Ok, thank you. You have definitely given me food for thought on OVP implementation for my board, I am not sure which way I will go with this but I have no more specific questions on it right now. I will respect your last point and not try a scheme with external hard pulldown of the ADM1275 GATE pin.
Let's close this thread I will click the above as answer and if I have some other detailed question in future can start another thread. Thanks again for all your help here, sincerely,