I'm trying to simulate the Power Good (PG) pin of the LT3094 in LTSpice. Using the built-in LT3094 test fixture with the default parameters, the voltage at PG jumps to the negative rail (-5V) after regulation is achieved. However, according to the block diagram of LT3094, this should not happen: the PG pin is connected to GND through an ideal diode, so it can go at most to one diode drop below GND. The Absolute Maximum Ratings also show it mustn't go below -0.3V with respect to GND. The block diagram shows that PG (an open collector) should go to some positive supply rail ("V+") through a pullup load - in the test fixture there is a 100k load, but it is connected to the negative rail.
All in all, I'm a bit confused whether it is the simulation model (&test fixture) that is in error, or perhaps the block diagram in the datasheet?