I'm trying to simulate the Power Good (PG) pin of the LT3094 in LTSpice. Using the built-in LT3094 test fixture with the default parameters, the voltage at PG jumps to the negative rail (-5V) after regulation is achieved. However, according to the block diagram of LT3094, this should not happen: the PG pin is connected to GND through an ideal diode, so it can go at most to one diode drop below GND. The Absolute Maximum Ratings also show it mustn't go below -0.3V with respect to GND. The block diagram shows that PG (an open collector) should go to some positive supply rail ("V+") through a pullup load - in the test fixture there is a 100k load, but it is connected to the negative rail.
All in all, I'm a bit confused whether it is the simulation model (&test fixture) that is in error, or perhaps the block diagram in the datasheet?
Hi,The simulation model(test fixture) on the LTspice sync released is wrong.The correct released LTSpice tool can be found online, please refer on the link below for the model.https://www.analog.com/en/products/lt3094.html#product-toolsPG pin should really be tied to a positve voltage (V+).I've already talked to the application engineer regarding this matter and this is already being handled by the LTspice modeling group. For now, please download the correct LTspice tool/model for this part on the link above.Regards,Ash
Thanks for the clarification!
Is the dissipation/current of the transistor (the collector of which is PG) limited internally in some way? I guess that's something to be wary about since it won't go into saturation.