Hello Analog Devices' support team,I recently started doing EVM testing for my personal project using your Hotswap component - ADM1272. During the component capability tests in FET SOA retention, results were discovered that do not converge to the data sheets and do not even converge on the theoretical calculations I have performed.In terms of information about the set-up:I fed the component at 30 V, limited the ISET current to 5 A (by placing the respective voltage divider in the relevant pin in the component),And I set the Load Resistor of 2.6 Ohm. According to the calculation by the way of operation based on the pin "ISTART" - we accepted, by applying the load (by switching on using another FET for switching operation) for current damping time of about 0.8 msecWhat we actually got:We got by measured the V_gate, V_ds, and the Output current - is 416usec delay in the operation of the gate of the FET, which in turn caused for delay in the operation of the current damping!
Moreover:We performed the same tests on different loads, including - shortcut (0 Ohm), 1.5 Ohm.In those test - we got as expected, and convergence for what we calculated.I would like to know if you can explain this phenomenon, and try to explain the above mismatch for this load.
I will try to upload lately the screenshot of the oscilloscope of the measurements
Thank you very much,Evyatar
Thanks for your detailed response.
We intend to use the device because it has very accurate current sensing according to its specs, much more than previous devices we used to use like LT4356. However, we use these devices to fit the stress to the SOA restrictions of our FETs. However, the 60uA regulation current you mentioned would pull down the maximum gate capacitance of the EVM's FETs in a few mili-seconds, while this is the total time of response we require in our FETs' SOA and therefore is too slow.
We used to get much quicker response time from former LT devices, and this device also shows three modes of pull-down current: regulation, slow and fast rates. Of course the fast mode is associated with the severe overcurrent event, but the datasheet doesn't mention how to use the slow rate. We require the output current to be under the required value (with 30mV sensing) at all times, perhaps except a few usecs like old LT devices. However we see about 400us in which the device lets whatever current the load pulls get through the FET.
Please advise how to get a quicker response from the device, and if masking the severe overcurrent with MCB is enough (logic would assume we will see a slower response). Also please advise how to use fast or slow pull-down currents for the gate.
In any case we would not wish to get output currents in values of 150% and further through our FETs. If this is not possible with this device we would like a recommendation for a supplement with similar accuracy but faster response. The device may be simpler in terms of PMBus commands and measurements.
The ADM1272 only has tao basic modes for pulling down the gate during operation, IGATEDN_REG and iGATEDN_FAST. IGATEDN_SLOW is for when ENABLE goes low. The speed with which the ADM1272 can pull down the gate of the FET in regulation is limited by the gate current. This cannot be changed. The only way to speed it up is to reduce the capacitance on that node. MCB will only slow down the circuit response to 1.5 and 0 ohm loads, so I don't think that is what you want.
You can try changing the severe OC threshold to 1.5x in the DEVICE_CONFIG[3:2] register. This will make the SOC response more sensitive so that it will fire during the 2.5 ohm load test.
If you want to continue using the LTC4356 for its faster gate response, you can add the LTC2946 current, power,energy monitor, and share the same sense resistor with the LTC4256. This will give you the digital monitoring that you need, as well as the hotswap performance that you prefer.