Hello Analog Devices' support team,I recently started doing EVM testing for my personal project using your Hotswap component - ADM1272. During the component capability tests in FET SOA retention, results were discovered that do not converge to the data sheets and do not even converge on the theoretical calculations I have performed.In terms of information about the set-up:I fed the component at 30 V, limited the ISET current to 5 A (by placing the respective voltage divider in the relevant pin in the component),And I set the Load Resistor of 2.6 Ohm. According to the calculation by the way of operation based on the pin "ISTART" - we accepted, by applying the load (by switching on using another FET for switching operation) for current damping time of about 0.8 msecWhat we actually got:We got by measured the V_gate, V_ds, and the Output current - is 416usec delay in the operation of the gate of the FET, which in turn caused for delay in the operation of the current damping!
Moreover:We performed the same tests on different loads, including - shortcut (0 Ohm), 1.5 Ohm.In those test - we got as expected, and convergence for what we calculated.I would like to know if you can explain this phenomenon, and try to explain the above mismatch for this load.
I will try to upload lately the screenshot of the oscilloscope of the measurements
Thank you very much,Evyatar
The ADM1272 has three factors that limit the start-up current and timing. The first, as you have observed, is the ISTART pin, which sets the start-up current limit, which is normally NOT engaged because it is a protective limit, and not approached if the load is behaving itself. The second limit is the DVDT pin, which sets the gate voltage ramp rate, and which is usually the primary method of limiting inrush current. The third is the ESTART pin, which functions as a timer during start-up current limiting (when the ISTART limit is activated). You didn't mention ESTART, so it is unclear how you programmed the 800us time limit. The usual way is to place a series R-C on the ESTART pin so that the pin voltages charges up and reaches 1V when the desired time-out elapses.
In your case, with 30V and 2.6 OHMS you should activate the ISTART current limit and charge up the ESTART pin. I assume from your description that this is happening within 416us. A larger ESTART capacitor will charge more slowly, of course, and may be what you need. A smaller ESTART series resistor will also help. For the 0 OHM and 1.5 OHM tests you may be activating the severe overcurrent limit, which shuts down the hotswap much more quickly, regardless of the ESTART pin.
In order for me to help more I will need to see your circuit schematic, including load capacitance and expected operating load currents.
Hello Nathan,First of all, thank you for your answer.Second, I think there was a little confuse: When I said there was a 416usec delay, and I was expected for 0.8msec for shutdown - I meant that after only 416usec of delay we saw a 0.8msec of current shutdown duration!which means, that there is a build in delay which is not clear how we got this delay!In the other measurements, we got convergence for the time we accepted, according to calculation on the R-C on the ESTART&EFAULT pins!
The whole calculations were based on the R-C nets which located on the EVM board.
I would like to know if you can again find an explanation for this unwilling phenomenon, and try to explain the above mismatch for this load.
Thank you very much,
It would be helpful if you could post a scope shot of the event that you are describing. That would help my understand and explain it.
Hello Nathan,I am uploading the screenshots of the Oscilloscope in two scenarios of measurements:1. Measure in 1.5Ohm load -
As you can see - we got a response time of 634usec - which by calculations, nearly close for what I accepted.On the other hand,2. Measure in 2.6Ohm load -
As you might see, there is about 400usec of delay, which in this time the current is flowing beyond the limit(very important notice: although you might think that the current is about 1.2A, because that is what we see from the scope; but - we use with probe with amplification - in X10! which means the current is actually in about 11A! beyond the limit for 400usec!), and only after this delay we can see the shutdown sequence (which takes in about 600usec more).thank you very much,Evyatar
Thank you for the plots. I think it is likely that your 0 ohm and 1.5 ohm loads are triggering the severe overcurrent response, which is very fast, and immediately turns off the FET by yanking down on the GATE pin, then releasing it for the slower control loop to regulate. Finally the EFAULT timer times out and turns off the output.
In the 2.5 ohm case you are probably just under the severe overcurrent threshold, and not activating the fast gate pulldown. This leaves the slower 60uA gate current to pull down the gate from its fully enhanced 12V overdrive to the point when the control loop enters active regulation.
If you plot the GATE node during these events you should see the effects that I mention. If you want to adjust this behavior you can program the DEVICE_CONFIG[3:1] bits to adjust the threshold and the fast recovery option. I suggest trying the 150% threshold first.
Thanks for your detailed response.
We intend to use the device because it has very accurate current sensing according to its specs, much more than previous devices we used to use like LT4356. However, we use these devices to fit the stress to the SOA restrictions of our FETs. However, the 60uA regulation current you mentioned would pull down the maximum gate capacitance of the EVM's FETs in a few mili-seconds, while this is the total time of response we require in our FETs' SOA and therefore is too slow.
We used to get much quicker response time from former LT devices, and this device also shows three modes of pull-down current: regulation, slow and fast rates. Of course the fast mode is associated with the severe overcurrent event, but the datasheet doesn't mention how to use the slow rate. We require the output current to be under the required value (with 30mV sensing) at all times, perhaps except a few usecs like old LT devices. However we see about 400us in which the device lets whatever current the load pulls get through the FET.
Please advise how to get a quicker response from the device, and if masking the severe overcurrent with MCB is enough (logic would assume we will see a slower response). Also please advise how to use fast or slow pull-down currents for the gate.
In any case we would not wish to get output currents in values of 150% and further through our FETs. If this is not possible with this device we would like a recommendation for a supplement with similar accuracy but faster response. The device may be simpler in terms of PMBus commands and measurements.
The ADM1272 only has tao basic modes for pulling down the gate during operation, IGATEDN_REG and iGATEDN_FAST. IGATEDN_SLOW is for when ENABLE goes low. The speed with which the ADM1272 can pull down the gate of the FET in regulation is limited by the gate current. This cannot be changed. The only way to speed it up is to reduce the capacitance on that node. MCB will only slow down the circuit response to 1.5 and 0 ohm loads, so I don't think that is what you want.
You can try changing the severe OC threshold to 1.5x in the DEVICE_CONFIG[3:2] register. This will make the SOC response more sensitive so that it will fire during the 2.5 ohm load test.
If you want to continue using the LTC4356 for its faster gate response, you can add the LTC2946 current, power,energy monitor, and share the same sense resistor with the LTC4256. This will give you the digital monitoring that you need, as well as the hotswap performance that you prefer.