Post Go back to editing

ADP1071-2 evm 36W 12.1 VOUT

Hello , I have some questions regarding adp1071-2 evalutaion board for 36 Watt (12V1 Output).

1) Is there a Ltspice model for the adp-1071-2 controller ? and if not , can you create one?

2) is there a minimum load condition for the adp-1071-2?

3)what is the meaning of "Forced ccm operation "? 

4) the datasheet represent application with input voltage between 4.5 to 60 volt.
 the block diagram of adp-1071-2 shows that VREG1 is created by the output of internal LDO to 8 V.
 how is it possible to create this 8 Volt at VREG1 if the input is less then 8 volt ( even 4.5 volt)?

5) how does the Rsoft start which is connected to the Gate at the primary influence the rate of duty cycle? it is only a "voltage divider" at the output of the controller?

thank you very much for your help!

  • Hi, Thanks for those questions, here please find some answers. 

    1). Yes, ADP1071-2 LTSPICE is available. Please update LTspice library to the latest one, and you can find ADP1071-2 example circuitry available. 

    2). No minimum load required for ADP1071-2.

    3). Generally, to save more power loss at light load, the converter will operate at discontinuous current mode (DCM), which means SR is turned off at light load. But for some application, specially noise sensitive application, customer don’t like DCM mode because it will have other frequency spectrum except the switching frequency. Then the converter will always work at continuous current mode (CCM), even at light load, which means SR is always turned on.  

    4). When the input voltage is below 8V, the LDO only have a small dropout voltage. The output voltage is very close to the input voltage of LDO. So the internal circuit still can work.

    5). The soft start sequence has two stages. The first stage is open loop soft start which is programmed by the resistor on the GATE pin. The second stage is close loop soft start which is programmed by the SS2 pin.

    BR, Justin