LT8609S ext clock using LTC6902 with SSFM

Looking to drive three LT8609S regulators from a LTC6902 with SSFM.  This appears fairly straight forward ... float DIV and PH (each bypassed with a 1nF capacitor), 10.5K SET for a 630kHz Fmax, 22K MOD for a 9.55% SSFM.  Connect OUT1 to the first LT8609S SYNC, OUT2 to the second LT8609S SYNC, and OUT3 to the third LT8609S SYNC.

The first question is regarding connecting the OUT to the SYNC.  Looking at how the LTC6902 is used to drive other LTC regulators I see in the LTM4627 datasheet that OUT is connected directly to SYNC, however the LTM4627 eval datasheet DC1668B shows each OUT to SYNC connection going through a 100 ohm resistor.

What is the significance of the 100 ohm resistor (EMI or something else)?

Is it recommended when using the LTC6902 to drive the LT8609S?

Also the LTC6902 notes that the SSFM frequency transitions are slowed by a 25kHz filter which suffices to work with regulators using a PLL so long as the PLL bandwidth exceeds that.

With Fmax set to 630kHz and 9.55% SSFM that means Fmin will be around 570kHz so allowing for tolerance it suggests setting the LT8609S Rt for 500kHZ (which also sets the slope compensation).

Will the LT8609S stay locked to the LTC6902S if the ext clock has SSFM?

Is there a limit to the SSFM spread to which the LT8609S will stay locked?

  • 0
    •  Analog Employees 
    on Aug 7, 2019 6:05 AM

    For LT8609S, SYNC frequency should be equal to or above RT set frequency.

  • Yep ... the datasheet mentions that.  The datasheet doesn't mention how well the device can track a changing frequency.  What are the restrictions regarding the LT8609S locking on to an external clock that uses SSFM? 

    How rapidly is the clock allowed to change?  The following is mentioned in the ltc6909 clock generator datasheet:

    Depending on the specific frequency synchronization method a switching regulator employs, the modulation rate must be within the synchronization capability of the regulator. Many regulators use a phase-locked loop (PLL) for synchronization. For these parts, the PLL loop filter should be designed to have sufficient capture range and bandwidth.

    Unfortunatey there doesn't seem to be any information in the LT8609S regarding the frequency synchronization method it employs.

  • 0
    •  Analog Employees 
    on Aug 12, 2019 11:21 PM in reply to jwehle

    External clock signal should be above RT pin set frequency and below 2.2MHz. The modulation depth should be within 20% of the sync frequency and within the RT set frequency and 2.2MHz. Modulation frequency can be very high up to 1/10th of the SYNC frequency. But need to be careful of the corresponding stability and noise issue.

    When using sync function, please choose a suitable inductor value to avoid subharmonic oscillation.

  • Thanks for the details.

    For the LT8609S is there any need for a resistor between the clock source
    and SYNC similar to the 100 ohm resistor which is on the LTM4627 eval board DC1668B-A?

  • 0
    •  Analog Employees 
    on Aug 27, 2019 2:30 AM in reply to jwehle

    I looked at DC1668B-A schematic and I don't see a 100 ohm resistor on the FSET pin. As long as you meet the sync signal requirement in page 13 of LTM4627 datasheet ( high level above 2V and a low level below 0.8V), resistor may or may not be required, 

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