I've already asked a very similar question concerning the LTM4644 and like to know whether the answer also applies to the LTM4650A.
I'd like to know whether there are any sequencing requirements for supplying an external clock to the LTM4650A MODE_PLLIN input.
The datasheet only states the frequency range (250kHz - 780kHz), voltage thresholds (1.6VIH, 1.0VIL), and that the initial frequency is determined by the fset resistor, but leaves some points open:
- Can a clock be supplied without VIN being present? The Absolute Maximum Ratings suggest no, since no INTVcc is not present in that case.
- If applying the Clock after VIN, are there any time constraints?
The following questions are to plan for failure modes:
- What happens if the clock to MODE_PLLIN is stopped (either at low, high or high-Z state) while outputs are enabled? Will the internal frequency determined by Resistor fset take over or will this result in outputs becoming unregulated? If the internal clock takes over, how fast does this happen?
I assume the "stop" value might affect the selected mode, but I am not certain whether this pin is only sampled at startup.
- What happens if the clock to MODE_PLLIN (within the specified frequency range) is applied when the LTM4650A is already running from the internal clock and has outputs enabled? Will this lead to (transient) changes in output voltages and/or outputs becoming unregulated?
Thanks for your assistance.