LTM4650A: Syncing to external clock: Power-up and failure modes

Hi,

I've already asked a very similar question concerning the LTM4644 and like to know whether the answer also applies to the LTM4650A.

I'd like to know whether there are any sequencing requirements for supplying an external clock to the LTM4650A MODE_PLLIN input.

The datasheet only states the frequency range (250kHz - 780kHz), voltage thresholds (1.6VIH, 1.0VIL), and that the initial frequency is determined by the fset resistor, but leaves some points open:

  1. Can a clock be supplied without VIN being present? The Absolute Maximum Ratings suggest no, since no INTVcc is not present in that case.
  2. If applying the Clock after VIN, are there any time constraints?

The following questions are to plan for failure modes:

  1. What happens if the clock to MODE_PLLIN is stopped (either at low, high or high-Z state) while outputs are enabled? Will the internal frequency determined by Resistor fset take over or will this result in outputs becoming unregulated? If the internal clock takes over, how fast does this happen?
    I assume the "stop" value might affect the selected mode, but I am not certain whether this pin is only sampled at startup.
  2. What happens if the clock to MODE_PLLIN (within the specified frequency range) is applied when the LTM4650A is already running from the internal clock and has outputs enabled? Will this lead to (transient) changes in output voltages and/or outputs becoming unregulated?

Thanks for your assistance.

  • 0
    •  Analog Employees 
    on Jul 12, 2019 11:26 PM

    Hi Christian,

    Please find my answers to your questions below. Thank you!

    1. Can a clock be supplied without VIN being present? The Absolute Maximum Ratings suggest no, since no INTVcc is not present in that case.

      Answer: Yes you can supply the clock without VIN being present. However, since there is no power to the IC, there will not be any switching even with an external clock input.

    2. If applying the Clock after VIN, are there any time constraints?
      Answer: No, there is no restrictions on when you apply the external clock.

    The following questions are to plan for failure modes:

    1. What happens if the clock to MODE_PLLIN is stopped (either at low, high or high-Z state) while outputs are enabled? Will the internal frequency determined by Resistor fset take over or will this result in outputs becoming unregulated? If the internal clock takes over, how fast does this happen?
      I assume the "stop" value might affect the selected mode, but I am not certain whether this pin is only sampled at startup.

      Answer: Yes, when the external clock is stopped during operation, the module will sync with the internal clock set by fset voltage. The output voltage will remain well regulated in less than 1ms in my test. It may be able to recover even faster as there is delay induced when I manually turn off the external output clock in the test setup. 

      When the external clock is removed, the MODE_PLLIN pin can be considered as floating and the corresponding mode will be in effect.

    2. What happens if the clock to MODE_PLLIN (within the specified frequency range) is applied when the LTM4650A is already running from the internal clock and has outputs enabled? Will this lead to (transient) changes in output voltages and/or outputs becoming unregulated?

      Answer: When the external clock is applied during operation, the module will sync with the external clock if it is within the range of 250 kHz - 780 kHz and meet the threshold requirement. The output voltage will remain well regulated after a fast transient.