we use 10 pcs of LTM4646 and 10 pcs of LTM4622 on a big power system. System requires External Synchronization Clock (800KHZ) for all DC/DC.
Now ONLY ONE sync clock 800KHZ is generated from FPGA, and feed to 20 DC/DC in daisy-chain topology. The output current driving strength of FPGA pins is about only 4mA, we are not sure whether it is enough to drive so many DC/DC sync pins.
So we hope to know the pin capacitance of SYNC pin (pin.F3 of LTM4646 and pin.C4) , and we can confirm the total load-capacitance, then decide wehter a buffer IC should be inserted.
Jittering at SW node will show at output voltage, causing much larger output voltage ripples.
The input resistance of the Mode_PLLIN pin for LTM4646 is 600kOhm. 4mA should be enough to drive 20 uModules. For 800kHz switching frequency, input capacitance of the model_PLLIN pins should not be an issue. We don't recommend daisy chain 20 uModules. Usually for daisy chain uModules, the clocking signals for 1st to 4th are pretty clean, but above 4th, the clocking signal starts to have jittering issues.
Would you please tell what performance would the jitter issue may affect after the 4th module of the daisy-chain? If it is important, we may need to insert buffer to generate more IC sync clock signals and ensure all modules are synchronized correctly.
by the way, would you please help look at this post on LTM4646 thermal design question?