LTC4418 with inrush current limiting and overlapping input ranges

I am designing a power input selector using the LTC4418 to select an input power source. The designed thresholds and hysteresis are as follows. Both inputs have inrush limiting circuitry on the FET gates due to the overlapping input voltage ranges.

Input 1: 24VDC AC-DC converter

  • UV1: 19.2V
  • OV2: 28.8V
  • hysteresis: 1V (UV1hys = 20.2V, OV1hys = 27.8V)

Input 2: 20-36VDC battery

  • UV2: 20.0V
  • OV2: 35.7V
  • hysteresis: 1V (UV2hys = 21.0V, OV2hys = 34.7V)

The entire circuit has been modeled in LTSpice. A screenshot is below and the LTSpice simulation file is also attached.

 ltc4418.zip

I am getting longer-than-expected transition time between input 2 being disconnected and input 1 being connected to the output when input 2 has a voltage higher than input 1. An example sequence is this. In this example, the extended transition time occurs between steps 7 and 8.

  1. Input 1 = input 2 = 0V
  2. Input 2 = 35.5V
  3. Input 2 becomes valid
  4. Input 2 is connected to the output
  5. Input 1 = 20.3V
  6. Input 1 becomes valid, which has priority over input 2
  7. Input 2 is disconnected from the output
  8. Input 1 is connected to the output

I have narrowed the cause down to the capacitance on node VS1 from capacitor C5. This capacitor value was chosen as 10 * Cs as suggested by the LTC4418 datasheet. The voltage on the VS1 net is 35V when input 1 becomes valid due to the body diode in P-FET M2 allowing Vout to charge it. Due to the selected inrush current limiting circuitry on node G1, G1 has a falling slew rate of about 0.24V/us. Since the voltage at VS1 matches Vout (35.5V) between steps 7 and 8 and VS1 must be discharged to 20.3V before the FETs on input 1 turn on, it takes an additional 65us for input 1 to become connected to the output. This results in a much larger than anticipated droop on Vout and additional inrush current during this transition.

Instead of adding additional capacitance on Vout to support this transition, I feel it is wiser to reduce the amount of time it takes for VS1 to discharge to 20.3V. I see two options and I'm not sure which is the right option.

  1. Reduce the capacitance of C5. This value was chosen as suggested by the datasheet for Cvs simply as 10 * Cs. There is no explanation for choosing this value and I am hesitant to reduce the value, but doing so does improve my issue.
  2. Add a bleeder path from VS1 to Vout to allow VS1 to discharge to Vout between steps 7 and 8. This could be implemented as a diode and series resistor between VS1 and Vout. This solution allows VS1 to track (Vout - Vf of the diode), nearly removing the additional 65us transition time caused by Cvs and reducing Vout droop.

Have you dealt with this issue before and how did you resolve it? Is one of the above two approaches preferred and an acceptable modification?

Thanks,

Robert