Please help me as I'm stuck!
I use LTC4162-L to charge a lithium battery and it works great!. I had a few prototype boards and every time I solder it myself. I've been having issues with the latest boards and the design and layout is the same as previous ones! It gives an output but it doesn't charge the battery. I tried resoldering a few boards multiple times but still haven't fixed it. Sometimes charging turns on but it turns off next time I plug in.
I took the good working board and non charging board and swapped all the components one by one and still good working board worked meaning that there wasn't a component issue.
I tried measuring the voltages around the IC to spot the difference and I noticed that pin 11 is 1.01V for a good working board and pin 11 oscillates from 0V to 2.4V slowly maybe once per second. What does it mean?
What are the other reasons for this IC not to charge? I use it standalone design without a micro so I can't debug it. Maybe its a thermal issue, I'm not sure.
I resoldered it multiple times now and its the same issue. The output still works even when I plug in the battery. Its just doesn't charge. I had a few times charging while testing so its not like it doesn't work all the time. Also the battery I'm using is low so it should charge. I also tried leaving it for like half an hour.
When you say that you swapped all components, do you mean all components besides the LTC4162? If that's the case, I would assume that the non-working unit has been damaged somehow and I would suspect that replacing it with a fresh unit would fix what you are seeing.
The RT pin should not be oscillating like that for any reason. Is there a valid resistor on it?
Just a quick update.
I tried by physically removing all the components from the non-working board that not part of the charging circuit and didn't help.
I tried swapping the ICs again with a working board and still working board works and non-working board doesn't charge.
These are strange problems that I've never seen before, probably caused by logic issues. Your schematic looks good but, after taking another look at the layout, I would guess that the cause is the routing and induced noise.
Take a look at the layout recommendations in the datasheet as well as the demo board layout and you'll notice that there is a lot that needs to be changed to get this to work right. I recommend you give it another shot and send it to me for review before going to fabrication. Feel free to copy the demo board layout as much as is applicable to your requirements.
Yeah, I suspect layout issue again.
I sent you my current layout. I compared my layout with demo board and I can see that mosfets are further away from the IC. I don't have enough space on my board. Also C15 Vbat capacitor is 90° and maybe C17 is further away from my board. The rest of it looks similar.
Do you think these layout differences could cause an issue?
Datasheet highlights that Vout capacitor needs to be close to the IC and I fixed that issue. Maybe its not happy with a battery capacitor now.
It looks much better, no problem with the FETs being closer.
This is a 2-layer board, right? The grounding makes me nervous because there is a lot of routing on the bottom of the PCB which cuts off the IC's GND paddle reference and creates longer paths for the circuitry. There is a GND pour on layer 2, right?
For all power connections, I recommend you via down to your GND pour for the GND connections. Feel free to connect direct to the IC paddle through grounded pins on layer 1 (like your routing of the bat capacitor's GND through the SYNC pin, that's good, but a via to the GND plane will help as well.
C17 needs a via that goes directly back to the IC paddle through the pour on layer 2.
Take another look for these techniques on the demo board layout and copy where you can. Also double-check the grounding. I'd like to see a version of the layout with the pour visible.
I sent you my current layout that battery detection doesn't work. Yes, it is a 2 layer board with a ground pour.
I will try and improve it and send you a new layout.
Sorry I meant C11 before. Why does C17 need a via if its on the top layer?
I sent you my updated layout. Please have a look.
I tried investigating by placing the capacitor Vbat C15 further and closer to the IC but didn't help. It only made a difference when I removed it. Then the battery voltage was 3V but still didn't detect the missing battery.
I also tried changing the switching frequency to see if it changes anything but it didn't make a any difference.
Do you think that I need to change it to 4 layer board?
Hi Emilija, I gave you some notes privately.
C17 (the 2P5VCC cap) needs a via because the best connection to the IC's GND reference (the GND paddle) is on layer 2. I mentioned this in my notes.
Switching to a 4 layer board would definitely be better if it is an option. It can be done with 2 layers but the layout will definitely require more planning without a dedicated GND layer.
If 4 layers is an option, just copy the demo board layout verbatim where you can. It is fine to move the PowerPath FETs closer, etc.
I sent you a message with a modified layout. Please have a look.
Hi, I made the design of the LTC4162 for two layers. But I have doubts with the ways used in pad number 29. And also some component locations, The idea is support between 0.5 to 0.8 amps for panel of 4w or 5w and battery with capacity of 4a, you could help me, I'm really new to the forum. The design image is as follows:
I can't be sure, but it looks like the pad is shorting to all the pins? Probably just a setting in the viewer but worth checking.
The actual pad looks good, and you properly used vias in the center of the pad to connect the GND.
The problem here is that your GND plane is choppy due to routing and this will cause noise which may cause the chip to malfunction. I recommend you go to a 4-layer board if possible and copy the demo board layout.
You might be ok here with your low charge current requirement, but I can't be sure and I would not take the risk.
Hi, thank you for you answer.If it is because of the remoteness of the image but the pad is not short. At this time it is almost impossible to change to a four-layer design. I changed the routing of a single track that is in the bottom layer to see if the noise can improve, what would have to change to be able to use a two layer PCB? Also I have more components in the PCB should I put a ferrite to separate GND?Pad number 29 must be soldier?