I am working on a capacitor-charger designed much similar to your evaluation board for the LT3751. My simulation-model: Schematic
I am experiencing that the FAULT-pin goes LOW right after I start a new charging cycle...
What I can see from the oscilloscope, the current-sources on OVLO1-2 / UVLO1-2 does not draw any current until the FAULT-pin goes LOW, meaning that the voltage on the OVLO/ UVLO - pins are at Vcc/V-trans at the time measuring over/under - voltages ... Which could be the reason why the system thinks over-voltage has occurred.
Picture of oscilloscope: signals (Blue = OVOL2 , Pink = Charge-pin (ramping up) , yellow = FAULT-pin)
Is this right? or could the chip be damaged? I do not see this behaviour in the simulation-model for the evaluation-kit.
The design is the same as for my previous prototype, but here i did not experience this issue.