I am working on a design with the LTM8063 on DC2494 evaluation board. I noticed that the ev board has a 100k pull-up to Vout since the LTM8063 PG is an open collector output. The PG signal goes to an input pin of an ATF1508AS CPLD, which may have 10uA input leakage. On 5V this can be modeled as a 155k resistor to the CPLD 5V.
Now, I want to build in some hardware protection in case the line between the LTM8063 PG and CPLD input goes high impedance. For this I would use a pull-down resistor, but due to the CPLD gate leakage this resistor should be arround 20k max. And that is not compatible with the 100k pull-up on the DC2494 board (a 5V PG signal would arrive as 1V at the CPLD input).Lowering the pull-up resistor on the DC2494 board is an option, the datasheet specifies a 150uA typical sink current on the LTM8063. Does this mean that the pull-up resistor should be min 33k?
I added an AD820 as non-inverting buffer between the circuits, with a 1M pull-down on the PG input signal.This works but is added circuitry, so the question whether this can be simplified by lowering the PG pull-up resistor remains.
You are right, the pull-up resistor should be min 33k for PG to operate normally.