On page 22 of the datasheet there are PCB layout recommendations. For the SOIC package the ground pour is shown as discontinuous between the thermal pad and the input capacitor. The attached image shows what I'm talking about; C1 is the input cap. Why is that break shown? On the same page the layout for the LFCSP package is also shown. It has a thermal pad as well, and there is no break in the ground pour. Is this a real thing, or a datasheet anomaly? There is no text in the datasheet talking about such a required break in the pour.
You may connect the connect the ground plane between the exposed pad and the input capacitor,