Problems with output current using LT3743

I took a close look at your schematic and could not see any major issues.  What is your load and what is your VIN voltage?  The LT3743 will regulate when either FB or SENSE+, SENSE- are at their thresholds.  We offer demonstration circuit DC1470A that will regulate a 4.5V LED at 20A with an input voltage at least 2V higher than the load up to 24V.  You can try simulating your circuit in LTspice as well.      

Hi ARad,

Thank you for the reply.

I am using a 12V DC 160 Watt power supply and the LED connected to the system is the CFT-90-WCS-X11-VB600 from Luminus devices. I have added a link to the datasheet below. I've also tried simulating the circuit in LTspice and this gives me the expected 25A of output current. The LTspice file is also placed below.

Kind regards,

WJK

Luminus_CFT-90-W_Datasheet-1511710.pdf

MyCircuit.zip

I took a look at your LTspice circuit and load and I still don't see major problems.  You used aluminum electrolytic capacitors for the output capacitors and we normally use lower ESR types like OSCON or hybrid polymer, perhaps in parallel with a couple ceramics for low noise.  My guess now is that your pcb layout has a problem.  I don't mind taking a look at pdfs of your pcb design.  It helps if the pdfs are clear and show the component names that match the schematic and also show interconnections between layers.  You can post the pdfs but it is probably better to have Technical Support route them to me. 

Hi ARad,

I would love it if you could take a look at the pcb design. I'll gladly have Technical Support route the pdf files to you. I can't find where I can upload files to technical support however. Should I request Technical support first and then will I be able to upload the files?

Any suggestions on improving the pcb design are welcome. (I'm new to this and still have a lot to learn.)

Thank you very much for your help.

Kind regards,
WJK

Go through Technical Support and tell them you want them to forward your schematic and layer pdfs to the factory applications engineer for the LT3743.  Technical Support will get the files to me.

I received the files of your pcb layout in addition to the schematic that I already reviewed.  Your pcb layout probably prevents your circuit from achieving full output current.  Demonstration circuit DC1470A for the LT3743 is so close to your pcb design in terms of the input and output connectors, why did you not just copy the DC1470A design?  I show the DC1470A top assembly in the image below.  The ceramic input capacitors need to be right next to the switching FETS on the pcb layout.  Then the switching FETs need gate drive traces with minimum loop area going all the way back to the VCC_INT capacitor.  Sorry I can't figure out an easy way to fix your pcb layout.  It is best to start with the DC1470A layout that works, and just make small changes to get your control signals in and out.  I liked the way you made layer 2 a complete ground plane - that is a good practice.

Hi ARad,

The design is indeed heavily based on the DC1470A board. Since I was running out of availbale area for the components I had to move some around. I'll try to make the next design resemble the DC1470A as closely as possible.

I also noticed that on the DC1470A most of the routing is done internally. Would you recommend doing this also in the board design. Like having layer 2 be the ground plane and place most of the routing in layer 3.

The board also has to have smaller dimensions than the DC1470A demo board. Could downsizing the board also be the cause of some problems and if so, what would be the smallest you would recommend. The layout you received was for a 50x50 mm board.

Kind regards,
WJK

I agree that you did save some of the DC1470 features.  The ceramic CIN caps need to be right across your switching FETs as I mentioned and there needs to be ground vias right at the source of your bottom switching FET.  Usually it is bad to route high speed traces on L4 - high speed traces normally work better if they are on either L1 or L3 so the traces are close to the L2 ground plane which is a signal return in many cases.  Some high speed traces do not use ground as a return, but in those cases the loop area still needs to be small and it is bad that vias add inductance going from the top layer to the bottom and back up. I usually keep the ic, the ceramics and at least one set of the switching FETs on the top layer.  Resistors, the inductor and the other FETs for this circuit can move to the bottom.