Am observing a strange behavior which am not able to characterize.
In ADCMP380 circuit (attached).
When i have VCC close to 4.6V and power the IC,OUT is high with in Pin Low,
When i have VCC close to 3.3V and power the IC,OUT is low with in Pin Low(expected ),and OUT goes high when IN goes > then VREF.
But after powering at VCC at 3.3V(in which OUT is low) i increase the VCC to 4.6V and OUT is still low.
SO above concludes the powerup @4.6V is causing the OUT to be released.
The EN pin has a internal pullup.
1. What is time after which the VREF is generated internally from VCC is applied?
2. How is the VREF generated internally like what method, using Zener?
3.What is the minimum rise time required for the IC or at which it was qualified after ASIC?
1. a 0.1uF 25V in the VCC pin is not shown in schematics.
2. VCC rise time is close to 50uS with no glicthes image added.
3.It is 3 AA battery powered to the VCC pin inserted to a battery holder which is the VCC pin of the IC.
Can somebody help to answer this?
A doc of Schematics, Layout is attached.
Image 3: VCC rise captured
Image 4:Low ringing setup:
VCC @ 4.6V(in Blue) with OUT going high in pink with IN low.(IN not shown in PIC)
DOC as in a working setup at VCC was kept at 3.3V and then increased to 4.6V