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ADCMP380 behaviour unable to understand

HI All,

Am observing a strange behavior which am not able to characterize.

In ADCMP380 circuit (attached).

When i have VCC close to 4.6V and power the IC,OUT is high with in Pin Low,

When i have VCC close to 3.3V and power the IC,OUT is low with in Pin Low(expected ),and OUT goes high when IN goes > then VREF.

But after powering at VCC at 3.3V(in which OUT is low) i increase the VCC to 4.6V and OUT is still low.

SO above concludes the powerup @4.6V is causing the OUT to be released.

The EN pin has a internal pullup.

Few questions:

1. What is time after which the VREF is generated internally from VCC is applied?

2. How is the VREF generated internally like what method, using Zener?

3.What is the  minimum rise time required for the IC or at which it was qualified after ASIC?

1. a 0.1uF 25V  in the VCC pin is not shown in schematics.

2. VCC rise time is close to 50uS with no glicthes image added.

3.It is 3 AA battery powered to the VCC pin inserted to a battery holder which is the VCC pin of the IC.

Can somebody help to answer this?

A doc of Schematics, Layout is attached.

Image 3: VCC rise captured

Image 4:Low ringing setup:

Image 1:

VCC @ 4.6V(in Blue) with OUT going high in pink with IN low.(IN not shown in PIC)

Image 1

Image 2

DOC as in a working setup at VCC was kept at 3.3V and then increased to 4.6V

Leak pad ic_doc.pdf

  • Video of what i described regarding VCC.

  • and more for your information the OUT pin of ADCMP380is not connected to MCU now and the MCU pin is lifted

  • Hello,

    Can you please do one more experiment, probe and capture the IN pin along with OUT when you are providing 4.6V to Vcc. I would recommend adding 0.1 µF decoupling capacitor to Vcc before the experiment.

    Also, is the issue always replicable when the ADCMP380is powered using 4.6V or is it intermittent?

  • The IN in with VCC is shown in image 1 and all the waveforms are captured with 0.1uF added as already indicated in point 1.

    Yes the issue is consistent and can be replicated consistently in the above board shown  .

  • It could have been due to sharp rise time on the VCC.

    It’s worth checking the position of the decoupling cap on VCC to make sure the current loop is short between vcc and ground.

  • The datasheet provides no details of it if any design considerations have to be taken in to account

  • Analog devices was able to recreate this issue. they do observe this behavior in the Evaluation board a RMA is in progress. Once we conclude on it with a boundary condition of VCC & Rise time required . i will close the Q&A