LT4356-3 anomalous behavior

Using the LT4356-3 device we find an its anomalous behavior: on an overvoltage event on the Vcc we obtain a final state of the device out of specification with a FLT signal low, but the OUT pin active (high).

What could determine such an anomalous behavior? Can the absence of a capacitor placed on the OUT pin (as indicated in some, but not alla diagrams of your application note) determine this behavior?

Thank you,

  • HI Nicola,

    The LTC4356-3 will pull the FLT# signal low when the TMR pin voltage reaches 1.25 V , whereas the Gate is pulled low when the TMR pin voltage reaches 1.35 V. This gives a constant "warning " time for the downstream control circuit / uC to do any necessary housekeeping functions before the supply is disconnected.

    If the TMR never reaches the 1.35V threshold , the gate will not be pulled low and output will be high. 

    Hope this clarifies the concern , let me know if you have any further questions.

    Best Regards,