LTM4644: Syncing to external clock: Power-up and failure modes

Hi,

I'd like to know whether there are any sequencing requirements for supplying an external clock to the LTM4644 CLKIN input.

The datasheet only states the frequency range (1MHz +- 30%), minimum voltage level (>2V), and that the PLL is disabled during start-up, but leaves some points open:

  1. What clock is used during start-up? Is it the internal 1MHz?
  2. Can a clock be supplied without VIN being present? The Absolute Maximum Ratings suggest no, since no INTVcc is not present in that case.
  3. If applying the Clock after VIN, are there any time constraints?

The following questions are to plan for failure modes:

  1. What happens if the clock to CLKIN is stopped while outputs are enabled (either at low, high or high-Z state)? Will the internal 1MHz take over or will this result in outputs becoming unregulated? If the 1MHz take over, how fast does this happen?
  2. What happens if the clock to CLKIN (within the specified frequency range) is applied when the LTM4644 is already running from the internal clock and has outputs enabled? Will this lead to (transient) changes in output voltages and/or outputs becoming unregulated?

Thanks for your assistance

  • 0
    •  Analog Employees 
    on Jan 16, 2019 12:39 AM

    Hi Christian 

    Any deviation of CLKIN with in the specified range 1MHz ± 30% will make LTM4644 go back to its internal CLK.

    Please see image below 

    ch1: CLKIN ch3:V1out switch node Ch4: V1out (AC coupled)

    regards,

    Mikee

  • Hi Mikee,

    thank you for your answer and the measurements you provided.

    Just to be clear, here are the conclusions I draw from your answer. Please correct me if anything is wrong.

    1. What clock is used during start-up? Is it the internal 1MHz?
      Yes, it is the internal 1MHz.
    2. Can a clock be supplied without VIN being present? The Absolute Maximum Ratings suggest no, since no INTVcc is not present in that case.
      VIN must be supplied first because it would violate the absolute maximum ratings otherwise.
    3. If applying the Clock after VIN, are there any time constraints?
      No, the PLL will lock onto any clock within 1MHz +-30% and with sufficient amplitude after startup is complete.
      There is no maximum delay to provide this clock after startup.

    The following questions are to plan for failure modes:

    1. What happens if the clock to CLKIN is stopped while outputs are enabled (either at low, high or high-Z state)? Will the internal 1MHz take over or will this result in outputs becoming unregulated? If the 1MHz take over, how fast does this happen?
      The LTM4644 will switch over to the internal 1MHz after about 20µs. The switching frequency will continually decrease during that interval down to 400kHz, but will not stop.
      Outputs may deviate slightly from their nominal values, but will not become completely unregulated.
    2. What happens if the clock to CLKIN (within the specified frequency range) is applied when the LTM4644 is already running from the internal clock and has outputs enabled? Will this lead to (transient) changes in output voltages and/or outputs becoming unregulated?
      The LTM4644 will lock onto the supplied clock. Outputs may slightly deviate from the nominal values during synchronization, but will not become completely unregulated.

    Please see image below 

    ch1: CLKIN ch3:V1out switch node Ch4: V1out (AC coupled)

    Thanks again for your assistance.

    Kind regards,

      Christian