LTC3871

Hello,

I would very much appreciate if one can go through the voltage loop of either configuration in the LTC3871, I find it very difficult to understand the flow described in the datasheet. 

Especially:

1. What is the mathematical expression of ICMP1?

2. What is VFLD?

3. What is IREV1,2?

Thanks!

Tom



Tags added
[edited by: tomur@post.bgu.ac.il at 4:13 PM (GMT 0) on 31 Dec 2018]
  • +1
    •  Analog Employees 
    on Jan 11, 2019 12:49 AM over 2 years ago
    1. The ICMP signal shown in the block diagram of Figure 10 is the sum of the AC and DC signals. Here is the equation:
      ICMP = (Low pass filtered DC signal) x4 + (AC signal) x1
    2. VFLD is a foldback control signal. The LTC3871 has foldback current limit when operating as a buck. It does not have foldback when operating as a boost. In foldback, the current limit threshold is progressively lowered as VLOW falls. The end result is reduced fault current and power losses. Foldback starts when VFBLOW falls below 80% of its nominal 1.2V value. See the Maximum Current Sense Threshold vs Feedback Voltage (DCR) curve on page 7 of the data sheet for more details.
    3. IREV1 & IREV2 are the reverse current sense comparators. When the LTC3871 is setup for discontinuous mode as a buck, the bottom MOSFET will turn-off once the inductor current drops below 0 Amps.
  • 0
    •  Analog Employees 
    on Jan 11, 2019 12:51 AM over 2 years ago

    The LTC3871 is basically a peak current mode buck controller with the ability to regulate the input voltage as a boost. The buck or boost operating mode is set with the BUCK pin. When the BUCK pin is high, the LTC3871 operates as a peak current mode buck. When the BUCK pin is low, the LTC3871 operates as a valley current mode boost. A summary of the two modes of operation follows – refer to the block diagram on page 10.

    Voltage and current regulation as a buck:
    The VLOW error amplifier senses the VLOW voltage through the FB divider tied to the VFBLOW pin. If the load on VLOW increases, VLOW drops which causes ITHLOW to rise. ITHLOW directly controls the inductor current through the current sense comparator.  When ITHLOW rises, the inductor current flowing towards VLOW rises and VLOW returns to regulation. If the load current rises above the threshold set by the ISET pin, the current loop will over-ride the voltage loop and the converter will become a current source.

    Voltage and current regulation as a boost:
    The VHIGH error amplifier senses the VHIGH voltage through the FB divider tied to the VFBHIGH pin. If the load on VHIGH increases, VHIGH drops which causes ITHHIGH to drop (not rise as would be the case for the VLOW error amplifier). ITHHIGH directly controls the inductor current through the current sense comparator.  When ITHHIGH drops, the inductor current flowing to VLOW also drops. This will cause the current flowing out of VHIGH to actually increase. This in turn permits VHIGH to return to regulation. As with operation as a buck, the current loop will over-ride the voltage loop once the load current exceeds the threshold set by the ISET pin.

     Note, the ISET voltage will need to be set above 1.25V when operating as a buck and below 1.25V when operating as a boost.

    Current sense comparator and switching logic for both the buck and boost operating conditions:
    At the start of each cycle, the rising edge of the internal clock sets an internal latch which turns on the top MOSFET. When the sum of the composite current sense signal (read next paragraph) and the slope compensation signals rises above either ITHLOW or ITHHIGH depending on the status of the BUCK pin, the latch is reset which turns off the top MOSFET.

    Current sense architecture:
    The LTC3871 uses a proprietary current sense architecture which amplifies the differential current sense signal to provide an enhanced signal to noise ratio. This allows the part to sense the voltage across low value sense resistors or sub-mOhm DCR inductors with high accuracy and low jitter. The internal current sense signal is re-created from the DC and AC current sense signals. The DC current sense voltage is the voltage from SNSD+ to SNS- and the AC voltage is the voltage from SNSA+ to SNS-. The DC signal is amplified by a factor of 4. The time constant for the AC filter is selected to be 5x smaller than the L/DCR time constant for sub-mOhm DCR sensing and 4x smaller than the L/Rsense time constant when sensing the voltage across a sense resistor. The amplified DC signal and the AC signal are summed together. The composite current sense signal will have a gain of 5 for sub-mOhm DCR sensing and a gain of 4 for the sense resistor setup. This composite signal is compared against either ITHLOW or ITHHIGH, depending on the operating mode, by the current sense comparator.