In the 8705/8705A data sheets, the rise and fall times for the gate drivers are noted as 20ns with a 3300pF load. Note 4 gives these times as the 10% - 90% times. Ergo, I can calculate the source and sink impedance via 20ns / 2.2 / 3300pF to get 2.75ohms. Since they are all specified at 20ns and 3300pF, the calculations would seem to indicate that the source and sink for each driver has been set to the same 2.75ohms.
However, I find that a lot of buck and/or boost controllers with internal FET drivers will typically have unbalanced impedances for source versus sink. For example, 2.0ohm source and 1.3ohm sink, etc.
Are the source and sink impedances really balanced in this chip on the gate drivers or did someone just not feel like putting the real numbers in and 20ns just sounded nice and round? I would love to learn that they are actually 2.5 / 1.5 or something like that to help with switch off times over on times which seems quite a common configuration.