LTC4162-L

I'm trying to create a stand alone battery charger for a single 18650 battery.

For this I created the Schematics and PCB found here.

But during the charging only charges with <1A (differential measured over the sense resistor <20mV/20mohm) instead of the calculated 1.6A in constant current mode with an average voltage of 3.90V.

Is there anything I missed while designing the schematic? Because I supply it currently with a lab power supply of 5V and 5A.

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  • Hello,

    I think the schematic looks good. You should make sure that you have some headroom between your input voltage and your battery. For example, be sure that your voltage is not drooping due to resistive losses by the point that it connects to the board.

    If you can read registers from the chip, that may help to determine what is going on.

    I do see some problems with the layout. For one thing, the thermal relief is not recommended as part of the switcher circuit, or for passing power. I recommend that you remove it from all components that will pass power and caps associated with that path.

    There is a recommended layout for this part which is on page 35 of the datasheet.

    This looks like a 2-layer board, correct? For this current level, that should be ok, but it looks like your IC's GND paddle does not have vias connecting it to a GND plane.

    I'm going to send you design files (privately) for our demo board which is releasing soon. You can use this as a reference.

    Regards,


    Zack

Reply
  • Hello,

    I think the schematic looks good. You should make sure that you have some headroom between your input voltage and your battery. For example, be sure that your voltage is not drooping due to resistive losses by the point that it connects to the board.

    If you can read registers from the chip, that may help to determine what is going on.

    I do see some problems with the layout. For one thing, the thermal relief is not recommended as part of the switcher circuit, or for passing power. I recommend that you remove it from all components that will pass power and caps associated with that path.

    There is a recommended layout for this part which is on page 35 of the datasheet.

    This looks like a 2-layer board, correct? For this current level, that should be ok, but it looks like your IC's GND paddle does not have vias connecting it to a GND plane.

    I'm going to send you design files (privately) for our demo board which is releasing soon. You can use this as a reference.

    Regards,


    Zack

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