ADP1071-1 : Start Up Behavior

I'm designing in ADP1071-1 PWM controller to regulate a two-switch flyback auxiliary power converter. As I'm going through the design I've encountered a few gray areas I was hoping to gain some insight on.

  1. The "GATE PIN" of the ADP1071-1 in my design is driving two inputs to a high side/low side driver which is high impedance input, I'm not utilizing the 1A driving capability of the PWM controller as the FETs are being driven by a dual driver external to the IC. How is this going to effect the "open loop slow start" I can still insert two gate resistors from GATE to GND for "Start-up", but does the equivalent resistance need to be exactly 10k, 22k, 47k, 100k or is it alright to be somewhere in between? Does the fact that I no longer have a low impedance path (capacitive-gate of MOSFET) influence the open loop slow start behavior?
  2. Could you provide some guideline as to sizing the capacitor on the secondary side soft-start PIN? Maybe in relation to the "open loop" soft-start before it takes over to achive a similar slope of Vout? I see the current source and can size the capacitor to achieve a certain time constant, but not sure what time constant makes sense.
  3. In order to complete the "Closed Loop" small signal analysis I generally need to know 3 parameters, Se, Sn and Gfb which translate to the slope of the slope compensator, slope of the sensed voltage and the small signal gain(mid-band gain) of the voltage feedback loop. I can calculate Se and Sn based on data provided in the datasheet, but not sure what Gfb is? I see a value of k = 0.5 and I think that may be it, but would you confirm? Or is the k=0 associated with the gain of the primary current sense signal?
  4. Are you planning on releasing an LTSpice simulation model for ADP1071-1/2 anytime soon? I know this question is already on the forum, but I'm wondering if someone is already working on it or is still undecided if generating a spice model is part of the scope.

Thank you!